Fixed bias can also be utilized for the enhancement-mode MOSFET, as is illustrated by the circuit of Fig. 4-25. The MOSFET is described by the drain characteristic of Fig. 4-9. Let R_1 = 60 kΩ, R_2 = 40 kΩ, R_D = 3 kΩ, R_L = 1 kΩ, V_{DD} = 15 \text {V, and} C_C → ∞. (*a*) Find V_{GSQ}. (*b*) Graphically determine V_{DSQ} and I_{DQ}.

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(*a*) Assume i_G = 0. Then, by (*4.3*),

R_G = \frac{R_1R_2}{R_1 + R_2} \quad \text{and} \quad V_{GG} = \frac{R_1}{R_1 + R_2} V_{DD} (*4.3*)

(*b*) The dc load line is constructed on Fig. 4-9 with v_{DS} intercept V_{DD} = 15 \text{V} and i_D intercept V_{DD}/R_L = 5 \text{mA}. The *Q*-point quantities can be read directly from projections back to the i_D and v_{DS} axes; they are V_{D S Q} \approx 11.3 \text{V} and I_{D Q} \approx 1.4 \text{mA}.

Question: 4.SP.19

(a) With negligible gate current, (4.2) gives
[l...

Question: 4.SP.18

(a) By KVL,
V_{GSQ1} = V_{GSQ2} + V_{DSQ1}[...

Question: 4.SP.17

By symmetry, I_{DQ1} = I_{DQ2}. KCL...

Question: 4.SP.16

Assume the devices are described by (4.2); then
[l...

Question: 4.SP.25

(a) The power supplied by the source V_{P...

Question: 4.SP.13

(a) Using the given data in (4.6) leads to
[late...

Question: 4.SP.12

(a) Since i_G = 0, V_{GSQ} = V_{GG}[/lat...

Question: 4.SP.11

(a) With negligible gate current, (4.3) leads t...

Question: 4.SP.10

(a) Solving (4.2) for v_{GS} and...

Question: 4.SP.27

(a) The dc load line has horizontal intercept [l...