For the FET series gate shown in Fig. 11.30.\ V_{s} = ±1 V,\ R_{s} = 50 Ω,\ R_{L} = 20 kΩ. The FET has the following parameters,\ V_{GS(OFF)max} = −10 V and\ R_{D(ON)} = 20 Ω. Calculate the voltage levels of the control signal,\ I_{D}, error due to\ R_{S} and error due to\ R_{D(ON)}.
The control signal should have a value\ V_{1} for\ Q_{1} to be ON.
Therefore,\ V_{1} = V_{s(peak)} = 1 V.
For\ Q_{1} to be OFF, the control signal should be\ –V_{2}
\ −V_{2} = −[V_{s(peak)} + V_{GS(OFF)max} + 1 V]
\ −V_{2} = −(1 + 10 + 1) = −12 V
\ I_{D} = \frac{V_{S}}{R_{S} + R_{D(ON)}+ R_{L}} = \frac{1}{50 + 20 + 20000} = 49.8 μA
\ I_{D}R_{S} = 49.8 × 10^{−6} × 0.05 × 10^{3} = 2.49 mV
Error due to\ R_{S} = \frac{2.49 mV}{ 1 V} × 100% = 0.249%
\ I_{D}R_{D(ON)} = 49.8 μA × 20 Ω = 0.996 mV
Error due to\ R_{D(ON)} = \frac{0.996 mV}{1 V} × 100% = 0.099%