Question 4.SP.18: For the series-connected identical JFETs of Fig. 4-23, IDSS ......

(a) By KVL,
V_{GSQ1} = V_{GSQ2} + V_{DSQ1}           (1)

But, since I_{DQ1} ≡ I_{DQ2}, (4.2) leads to
i_D = I_{DSS} \left( 1 + \frac{v_{GS}}{V_{p0}} \right)^2              (4.2)
I_{DSS} \left(1 + \frac{V_{GSQ1}}{V_{p0}} \right)^2 = I_{DSS} \left(1 + \frac{V_{GSQ2}}{V_{p0}} \right)^2

or,          V_{GSQ1} = V_{GSQ2}           (2)

Substitution of (2) into (1) yields V_{DSQ1} = 0.

(b) With negligible gate current, KVL applied around the lower gate-source loop requires that V_{GSQ1} = -I_{DQ1}R_S.    Substituting into (4.2) and rearranging now give a quadratic in I_{DQ1}:
I^2_{DQ1}  –  \left(\frac{V_{p0}}{R_S}\right)^2 \left(\frac{1}{I_{DSS}} + \frac{2R_S}{V_{p0}} \right) I_{DQ1} + \left(\frac{V_{p0}}{R_S}\right)^2 = 0        (3)

Substitution of known values gives
I^2_{DQ1}  –  4.5 × 10^{-3}I_{DQ1} + 4 × 10^{-6} = 0

from which we obtain I_{DQ1} = 3.28  \text{mA} and 1.22  \text{mA}.    The value I_{DQ1} = 3.28  \text{mA} would result in V_{GSQ1} < -V_{p0}, so that value is extraneous.    Hence, I_{DQ1} = 1.22  \text{mA}.

(c)          V_{GSQ1} = -I_{DQ1}R_S = -(1.22 × 10^{-3})(2 × 10^{3}) = -2.44  \text{V}

(d) From (1) with V_{DSQ1} = 0, we have V_{GSQ2} = V_{GSQ1} = -2.44  \text{V}.

(e) By KVL,
V _{DSQ2} = V_{DD}  –  V_{DSQ1}  –  I_{DQ1}(R_S + R_D) = 15  –  0  –  (1.22 × 10^{-3})(2 × 10^{3} + 5 × 10^{3}) = 6.46  \text{V}