Gate current is negligible for the *p*-channel JFET of Fig. 4-17. If V_{DD} = -20 \text{V}, I_{DSS} = -10 \text{mA}, I_{DQ} = -8 \text{mA}, V_{p0} = -4 \text{V}, R_S = 0, and R_D = 1.5 kΩ, find (*a*) V_{GG} and (*b*) V_{DSQ}.

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(*a*) Solving (*4.2*) for v_{GS} and substituting *Q*-point conditions yield

i_D = I_{DSS} \left( 1 + \frac{v_{GS}}{V_{p0}} \right)^2 (*4.2*)

V_{GSQ} = V_{p0} \left[ \left(\frac{I_{DQ}}{I_{DSS}} \right)^{1/2} – 1 \right] = -4 \left[ \left(\frac{-8}{-10} \right)^{1/2} – 1 \right] = 0.422 \text{V}

With negligible gate current, KVL requires that V_{GG} = V_{GSQ} = 0.422 \text{V}.

(*b*) Applying KVL around the drain-source loop gives

V_{DSQ} = V_{DD} – I_{DQ}R_D = (-20) – (-8 × 10^{-3})(1.5 × 10^{3}) = -8 \text{V}

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