The dc load line is constructed on Fig. 4-9(b) with v_{DS} intercept of V_{DD} = 15  \text{V} and i_D intercept of V_{DD}/R_L = 5  \text{mA}.    With gate current negligible (see Section 4.3), no voltage appears across R_F, and so V_{GS} = V_{DS}.    The drain-feedback bias line of Fig. 4-9(b) is the locus of all points for which V_{GS} = V_{DS}.    Since the Q point must lie on both the dc load line and the drain-feedback bias line, their intersection is the Q point.    From Fig. 4-9(b), I_{DQ} ≈ 2.65  \text{mA} and V_{DSQ} = V_{GSQ} ≈ 6.90  \text{V}.