# Question 3.SP.33: The amplifier of Fig. 3-27 uses an Si transistor for which V......

The amplifier of Fig. 3-27 uses an Si transistor for which $V_{BEQ} = 0.7 \text{V}$. Assuming that the collector-emitter bias does not limit voltage excursion, classify the amplifier according to Table 3-4 if    (a) $V_B = 1.0 \text{V}$ and $v_S = 0.25 \cos ωt \text{V}$,    (b) $V_B = 1.0 \text{V}$ and $v_S = 0.5 \cos ωt \text{V}$,    (c) $V_B = 0.5 \text{V}$ and $v_S = 0.6 \cos ωt \text{V}$,    (d) $V_B = 0.7 \text{V}$ and $v_S = 0.5 \cos ωt \text{V}$.

Table 3-4

 Class Percentage of Active-Region Signal Excursion A 100 AB between 50 and 100 B 50 C less than 50
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As long as $v_S + V_B > 0.7 \text{V}$ , the emitter-base junction is forward-biased; thus classification becomes a matter of determining the portion of the period of $v_S$ over which the above inequality holds.

(a)    $v_S + V_B ≥ 0.75 \text{V}$  through the complete cycle; thus the transistor is always in the active region, and the amplifier is of class A.

(b)    $0.5 ≤ v_S + V_B ≤ 1.5 \text{V}$ ; thus the transistor is cut off for a portion of the negative excursion $v_S$. Since cutoff occurs during less than 180°, the amplifier is of class AB.

(c)    $-0.1 ≤ v_S + V_B ≤ 1.1 \text{V}$, which gives conduction for less than 180° of the period of $v_S$, for class C operation.

(d)   $v_S + V_B ≥ 0.7 \text{V}$  over exactly 180° of the period of $v_S$, for class B operation.

Question: 3.SP.15

## Find the value of the emitter resistor RE that, when added to the Si transistor circuit of Fig. 3-17, would bias for operation about VCEQ = 5 V. Let ICEO = 0, β = 80, RF = 220 kΩ, RC = 2 kΩ, and VCC = 12 V. ...

Application of KVL around the transistor terminals...
Question: 3.SP.14

## For the amplifier of Fig. 3-17, CC = 100 μF, RF = 180 kΩ, RL = 2 kΩ, RS = 100 kΩ, VCC = 12 V, and vS = 4 sin(20 × 10³πt) V. The transistor is described by the default npn model of Example 3.2. Use SPICE methods to (a) determine the quiescent values (IBQ, ICQ, VBEQ, VCEQ) and (b) plot the input and ...

(a) The netlist code that follows models the circu...
Question: 3.SP.13

## The circuit of Fig. 3-17 uses current- (or shunt-) feedback bias. The Si transistor has ICEO ≈ 0, VCEsat ≈ 0, and hFE = 100. If RC = 2 kΩ and VCC = 12 V, size RF for ideal maximum symmetrical swing (that is, location of the quiescent point such that VCEQ = VCC/2). ...

Application of KVL to the collector-emitter bias c...
Question: 3.SP.12

## Collector characteristics for the Ge transistor of Fig. 3-15 are given in Fig. 3-16. If VEE = 2 V, VCC = 12 V, and RC = 2 kΩ, size RE so that VCEQ = -6.4 V. ...

We construct, on Fig. 3-16, a dc load line having ...
Question: 3.SP.10

## The Si transistor of Fig. 3-14 is biased for constant base current. If β = 80, VCEQ = 8 V, RC = 3 kΩ, and VCC = 15 V, find (a) ICQ and (b) the required value of RB. (c) Find RB if the transistor is a Ge device. ...

(a) By KVL around the collector-emitter circuit, [...
Question: 3.8

## The signal source switch of Fig. 3-9(a) is closed, and the transistor base current becomes iB = IBQ + ib = 40 + 20 sin ωt μA  The collector characteristics of the transistor are those displayed in Fig. 3-9(b). If VCC = 12 V and Rdc = 1 kΩ, graphically determine (a) ICQ and VCEQ, (b) ic and vce, and ...

(a)   The dc load line has ordinate intercept [lat...
Question: 3.7

## For the transistor circuit of Fig. 3-8(a), R1 = 1 kΩ, R2 = 20 kΩ, RC = 3 kΩ, RE = 10 Ω, and VCC = 15 V. If the transistor is the generic npn transistor of Example 3.3, use SPICE methods to determine the quiescent values IBQ, VBEQ, ICQ, and VCEQ. ...

The netlist code below models the circuit. EX3_...
Question: 3.SP.28

## In the circuit of Fig. 3-8(a), RC = 300 Ω, RE = 200 Ω, R1 = 2 kΩ, R2 = 15 kΩ, VCC = 15 V, and β =  110 for the Si transistor. Assume that ICQ ≈ IEQ and VCEsat ≈ 0. Find the maximum symmetrical swing in collector current (a) if an ac base current is injected, and (b) if VCC is changed to 10 V but ...

(a)  From (3.5) and (3.7), I_{CQ} ≈ I_{EQ} ...
Question: 3.SP.27

## In the circuit of Fig. 3-10(a), the transistor is a Si device, RE = 200 Ω, R2 = 10R1 = 10 kΩ, RL = RC = 2 kΩ, β = 100, and VCC = 15 V. Assume that CC and CE are very large, that VCEsat ≈ 0, and that iC = 0 at cutoff. Find (a) ICQ, (b) VCEQ, (c) the slope of the ac load line, (d) the slope of the dc ...

(a)   Equations (3.5) and (3.7), give I_{CQ...