# Question 3.8: The signal source switch of Fig. 3-9(a) is closed, and the t......

The signal source switch of Fig. 3-9(a) is closed, and the transistor base current becomes

$i_B = I_{BQ} + i_b = 40 + 20 \sin ωt μ\text{A}$

The collector characteristics of the transistor are those displayed in Fig. 3-9(b).   If $V_{CC} = 12 \text{V}$ and $R_{dc} = 1 kΩ$, graphically determine (a) $I_{CQ}$ and $V_{CEQ}$, (b) $i_c$ and $v_{ce}$, and (c) $h_{FE}(= β)$ at the $Q$ point.

Step-by-Step
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(a)   The dc load line has ordinate intercept $V_{CC}/R_{dc} = 12 \text{mA}$ and abscissa intercept $V_{CC} = 12 \text{V}$ and is constructed on Fig. 3-9(b).    The $Q$ point is the intersection of the load line with the characteristic curve $i_B = I_{BQ} = 40 μ\text{A}$.    The collector quiescent quantities may be read from the axes as $I_{CQ} = 4.9 \text{mA}$ and $V_{CEQ} = 7.2 \text{V}$.

(b)   A time scale is constructed perpendicular to the load line at the $Q$ point, and a scaled sketch of $i_b = 20 \sin ωt μ\text{A}$ is drawn [see Fig. 3-9(b)] and translated through the load line to sketches of $i_c$ and $v_{ce}$. As $i_b$ swings $±20 μ\text{A}$ along the load line from points $a$ to $b$, the ac components of collector current and voltage take on the values
$i_c = 2.25 \sin ωt \text{mA} \quad \text{and} \quad v_{ce} = -2.37 \sin ωt \text{V}$
The negative sign on $v_{ce}$ signifies a 180° phase shift.

(c)   From (3.2) with $I_{CEO} = 0$ [the $i_B = 0$ curve coincides with the $v_{CE}$ axis in Fig. 3-9(b)],
$β(≡ h_{FE}) ≡ \frac{α}{1 – α} ≡ \frac{I_C – I_{CEO}}{I_B}$        (3.2)
$h_{FE} = \frac{I_{CQ}}{I_{BQ}} = \frac{4.9 × 10^{-3}}{40 × 10^{-6}} = 122.5$

It is clear that amplifiers can be biased for operation at any point along the dc load line.    Table 3-4 shows the various classes of amplifiers, based on the percentage of the signal cycle over which they operate in the linear or active region.

Table 3-4

 Class Percentage of Active-Region Signal Excursion A 100 AB between 50 and 100 B 50 C less than 50

Question: 3.SP.15

## Find the value of the emitter resistor RE that, when added to the Si transistor circuit of Fig. 3-17, would bias for operation about VCEQ = 5 V. Let ICEO = 0, β = 80, RF = 220 kΩ, RC = 2 kΩ, and VCC = 12 V. ...

Application of KVL around the transistor terminals...
Question: 3.SP.14

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(a) The netlist code that follows models the circu...
Question: 3.SP.13

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Question: 3.SP.12

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We construct, on Fig. 3-16, a dc load line having ...
Question: 3.SP.10

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(a) By KVL around the collector-emitter circuit, [...
Question: 3.7

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The netlist code below models the circuit. EX3_...
Question: 3.SP.28

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(a)  From (3.5) and (3.7), I_{CQ} ≈ I_{EQ} ...
Question: 3.SP.27

## In the circuit of Fig. 3-10(a), the transistor is a Si device, RE = 200 Ω, R2 = 10R1 = 10 kΩ, RL = RC = 2 kΩ, β = 100, and VCC = 15 V. Assume that CC and CE are very large, that VCEsat ≈ 0, and that iC = 0 at cutoff. Find (a) ICQ, (b) VCEQ, (c) the slope of the ac load line, (d) the slope of the dc ...

(a)   Equations (3.5) and (3.7), give I_{CQ...
Question: 3.SP.21

## The Si Darlington transistor pair of Fig. 3-21 has negligible leakage current, and β1 = β2 = 60. Let R1 = R2 = 1 MΩ, RE = 500 Ω, and VCC = 12 V. Find (a) IEQ2, (b) VCEQ2, and (c) ICQ1. ...

As long as v_S + V_B > 0.7  \text{V}[/la...