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Chapter 7

Q. 7.11

It is required to design the circuit of Fig. 7.48(c) to establish a dc drain current ID = 0.5 mA. The MOSFET is specified to have Vt = 1 V and k_{n}^{′} W/L = 1 mA/V². For simplicity, neglect the channel-length modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15 V. Calculate the percentage change in the value of ID obtained when the MOSFET is replaced with another unit having the same k_{n}^{′}W/L but Vt = 1.5 V.

Figure 7.48

Step-by-Step

Verified Solution

As a rule of thumb for designing this classical biasing circuit, we choose RD and RS to provide one-third of the power-supply voltage VDD as a drop across each of RD, the transistor (i.e., VDS), and RS . For VDD = 15 V, this choice makes VD = +10 V and VS = +5 V. Now, since ID is required to be 0.5 mA, we can find the values of RD and RS as follows:

R_{D} = \frac{V_{DD}  –  V_{D}}{I_{D}} = \frac{15  –  10}{0.5} = 10  kΩ

R_{S} = \frac{V_{S}}{R_{S}} = \frac{5}{0.5 } = 10  kΩ

The required value of VGS can be determined by first calculating the overdrive voltage VOV from

I_{D} = \frac{1}{2}k_{n}^{′}(W/L)V_{OV}^{2}

0.5 = \frac{1}{2} × 1 × V_{OV}^{2}

which yields VOV = 1 V, and thus,

VGS = Vt + VOV = 1 + 1 = 2 V

Now, since VS = +5 V, VG must be

VG = VS + VGS =  5 + 2 = 7 V

To establish this voltage at the gate we may select RG1 = 8 MΩ and RG2 = 7 MΩ. The final circuit is shown in Fig. 7.49. Observe that the dc voltage at the drain (+10 V) allows for a positive signal swing of +5 V (i.e., up to VDD) and a negative signal swing of 4 V [i.e., down to (VG – Vt )].

If the NMOS transistor is replaced with another having Vt = 1.5 V, the new value of ID can be found as follows:

I_{D} = \frac{1}{2} × 1 × (V_{GS}  –  1.5)^{2}                        (7.138)

VG = VGS + IDRS

7 = VGS + 10 ID                        (7.139)

Solving Eqs. (7.138) and (7.139) together yields

ID = 0.455 mA

Thus the change in ID is

ΔID = 0.455 − 0.5 = −0.045 mA

which is \frac{-0.045}{0.5} × 100 = −9 % change.

Figure 7.49