## Textbooks & Solution Manuals

Find the Source, Textbook, Solution Manual that you are looking for in 1 click.

## Tip our Team

Our Website is free to use.
To help us grow, you can support our team with a Small Tip.

## Holooly Tables

All the data tables that you may search for.

## Holooly Help Desk

Need Help? We got you covered.

## Holooly Arabia

For Arabic Users, find a teacher/tutor in your City or country in the Middle East.

Products

## Textbooks & Solution Manuals

Find the Source, Textbook, Solution Manual that you are looking for in 1 click.

## Holooly Arabia

For Arabic Users, find a teacher/tutor in your City or country in the Middle East.

## Holooly Help Desk

Need Help? We got you covered.

## Q. 16.8

Objective: Calculate the power dissipation in a CMOS inverter.

Consider a CMOS inverter with a load capacitance of $C_{L} = 2 pF$ biased at $V_{DD} = 5 V$. The inverter switches at a frequency of f = 100 kHz.

## Verified Solution

From Equation (16.52), power dissipation in the CMOS inverter is

$P = f E_{T} = f C_{L} V^{2}_{DD}$           (16.52)

$P = f C_{L} V^{2}_{DD} = (10^{5})(2 × 10^{−12})(5)^{2} ⇒ 5 µW$
Comment: Previously determined values of static power dissipation in NMOS inverters were on the order of 500 µW; therefore, power dissipation in a CMOS inverter is substantially smaller. In addition, in most digital systems, only a small fraction of the logic gates change state during each clock cycle; consequently, the power dissipation in a CMOS digital system is substantially less than in an NMOS digital system of similar complexity.