Assuming that the transistor is biased in the saturation region, we have I_{DQ} = K_{p}(V_{SG} + V_{T P})^{2} . Solving for the source-to-gate voltage, we find the required value of source-to-gate voltage to be
V_{SG} = \sqrt{\frac{I_{DQ}}{K_{p}}}  –  V_{T P} = \sqrt{\frac{100}{100}}  −  (−0.4)
or
V_{SG} = 1.4  V
We may note that the design value of
V_{SDQ} = 3  V \gt V_{SDQ} (sat) = V_{SGQ} + V_{T P} = 1.4  −  0.4 = 1  V
so that the transistor will be biased in the saturation region.
The voltage at the gate with respect to ground potential is found to be
V_{G} = V^{+}  −  V_{RS}  −  V_{SG} = 2.5  −  0.8  −  1.4 = 0.3  V
With V_{G} \gt 0, the resistor R_{2} will be the larger of the two bias resistors, so set R_{2} = 200  k\Omega. The current through R_{2} is then
I_{Bias} = \frac{V_{G}  −  V^{−}}{R_{2}} = \frac{0.3  −  (−2.5)}{200} = 0.014  mA
Since the current through R_{1} is the same, we can find the value of R_{1} to be
R_{1} = \frac{V^{+}  −  V_{G}}{I_{Bias}} = \frac{2.5  −  0.3}{0.014}
which yields
R_{1} = 157  k \Omega

The source resistor value is found from
R_{S} = \frac{V_{RS}}{I_{DQ}} = \frac{0.8}{0.1}
or
R_{S} = 8  k\Omega
The voltage at the drain terminal is
V_{D} = V^{+}  −  V_{RS}  −  V_{SD} = 2.5  −  0.8  −  3 = −1.3  V
Then the drain resistor value is found as
R_{D} = \frac{V_{D}  −  V^{−}}{I_{DQ}} = \frac{−1.3  −  (−2.5)}{0.1}
or
R_{D} = 12  k \Omega
Trade-offs: If the conduction parameter K_{p} varies by ±5%, the quiescent drain current I_{DQ} and the source-to-drain voltage V_{SDQ} will change. Using the resistor values found in the previous design, we find the following:

Comment: We may note that the variation in the Q-point values is smaller that the variation in K_{p}. Including the source resistor R_{S} tends to stabilize the Q-point.