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Chapter 3

Q. 3.22

Objective: Design a circuit with an enhancement-mode MESFET.

Consider the circuit shown in Figure 3.65(a). The transistor parameters are: V_{T N} = 0.24  V, K_{n} = 1.1  mA/V² , and λ = 0. Let R_{1} + R_{2} = 50  kΩ. Design the circuit such that V_{GS} = 0.50  V and V_{DS} = 2.5  V.

3.65

Step-by-Step

Verified Solution

From Equation (3.38(a)) the drain current is
I_{D} = K_{n}(V_{GS}  −  V_{T N})^{2} = (1.1)(0.5  −  0.24)^{2} = 74.4  µA
From Figure 3.65(b), the voltage at the drain is
V_{D} = V_{DD}  −  I_{D} R_{D} = 4  −  (0.0744)(6.7) = 3.5  V
Therefore, the voltage at the source is
V_{S} = V_{D}  −  V_{DS} = 3.5  −  2.5 = 1  V
The source resistance is then
R_{S} = \frac{V_{S}}{I_{D}} = \frac{1}{0.0744} = 13.4  k \Omega
The voltage at the gate is
V_{G} = V_{GS} + V_{S} = 0.5 + 1 = 1.5  V

Since the gate current is zero, the gate voltage is also given by a voltage divider equation, as follows:
V_{G} = \left( \frac{R_{2}}{R_{1}  +  R_{2}} \right) (V_{DD})
or

1.5 = \left( \frac{R_{2}}{50} \right) (4)
which yields
R_{2} = 18.75  k\Omega
and
R_{1} = 31.25  k\Omega
Again, we see that
V_{DS} = 2.5  V \gt V_{GS}  −  V_{T N} = 0.5  −  0.24 = 0.26  V
which confirms that the transistor is biased in the saturation region, as initially assumed.
Comment: The dc analysis and design of an enhancement-mode MESFET circuit is similar to that of MOSFET circuits, except that the gate-to-source voltage of the MESFET must be held to no more than a few tenths of a volt.