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## Q. 3.20

Objective: Design a JFET circuit with a voltage divider biasing circuit. Consider the circuit shown in Figure 3.61(a) with transistor parameters $I_{DSS} = 12 mA, V_{P} = −3.5 V$, and λ = 0. Let $R_{1} + R_{2} = 100 kΩ$. Design the circuit such that the dc drain current is $I_{D} = 5 mA$ and the dc drain-to-source voltage is $V_{DS} = 5 V$.

## Verified Solution

Assume the transistor is biased in the saturation region. The dc drain current is then given by
$I_{D} = I_{DSS} \left( 1 − \frac{V_{GS}}{V_{P}} \right)^{2}$
Therefore,
$5 = 12 \left(1 − \frac{V_{GS}}{(−3.5)} \right)^{2}$
which yields
$V_{GS} = −1.24 V$
From Figure 3.61(b), the voltage at the source terminal is
$V_{S} = I_{D} R_{S} − 5 = (5)(0.5) − 5 = −2.5 V$
which means that the gate voltage is
$V_{G} = V_{GS} + V_{S} = −1.24 − 2.5 = −3.74 V$
We can also write the gate voltage as
$V_{G} = \left(\frac{R_{2}}{R_{1} + R_{2}} \right) (10) − 5$
or
$−3.74 = \frac{R_{2}}{100} (10) − 5$

Therefore,
$R_{2} = 12.6 k \Omega$
and
$R_{1} = 87.4 k\Omega$
The drain-to-source voltage is
$V_{DS} = 5 − I_{D} R_{D} − I_{D} R_{S} − (−5)$
Therefore,
$R_{D} = \frac{10 − V_{DS} − I_{D} R_{S}}{I_{D}} = \frac{10 − 5 − (5)(0.5)}{5} = 0.5 k \Omega$
We also see that
$V_{DS} = 5 V\gt V_{GS} − V_{P} = −1.24 − (−3.5) = 2.26 V$
which shows that the JFET is indeed biased in the saturation region, as initially assumed.
Comment: The dc analysis of the JFET circuit is essentially the same as that of the MOSFET circuit, since the gate current is assumed to be zero.