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## Q. 4.11

Objective: Design an NMOS amplifier with an enhancement load to meet a set of specifications.

Specifications: An NMOS amplifier with the configuration shown in Figure 4.39(a) is to be designed to provide a small-signal voltage gain of $|A_{v}| = 10$. The Q-point is to be in the center of the saturation region. The circuit is to be biased at $V_{D D} = 5 V$.
Choices: NMOS transistors with parameters $V_{T N} = 1 V, k´_{n} = 60 μA/V^{2}$ , and λ = 0 are available. The minimum width-to-length ratio is $(W/L)_{min} = 1$. Tolerances of ±5 percent in the $k´_{n}$ and $V_{TN}$ parameters must be considered.

## Verified Solution

(ac design): From Equation (4.50), we have
$|A_{v}| = 10 = \sqrt{\frac{(W/L)_{D}}{(W/L)_{L}}}$
which can be written as
$\left( \frac{W}{L} \right)_{D} = 100 \left( \frac{W}{L} \right)_{L}$
If we set $(W/L)_{L} = 1$, then $(W/L)_{D} = 100$.
(dc design): Setting the currents in the two transistors equal to each other (both transistors biased in saturation region), we have
$i_{D D} = K_{n D} (v_{G S D} − V_{T N D})^{2} = i_{DL} = K_{nL} (v_{G SL} − V_{T N L})^{2}$
From Figure 4.39(a), we see that $v_{G SL} = V_{D D} − v_{O}$ . Substituting, we have
$K_{n D} (v_{G S D} − V_{T N D})^{2} = K_{nL} (V_{D D} − v_{O} − V_{T N L} )^{2}$
Solving for $v_{O}$, we have
$v_{O} = (V_{D D} − V_{T N L} ) − \sqrt{\frac{K_{n D}}{K_{nL}} } (v_{G S D} − V_{T N D} )$
At the transition point,
$v_{Ot} = v_{DS D} (sat) = v_{G S Dt} − V_{T N D}$
where $v_{GSDt}$ is the gate-to-source voltage of the driver at the transition point. Then
$v_{GSDt} − V_{T N D} = (V_{D D} − V_{T N L} ) − \sqrt{\frac{K_{n D}}{K_{nL}}} (v_{G S Dt} − V_{T N D} )$
Solving for $v_{GSDt}$ , we obtain
$v_{GSDt} = \frac{(V_{D D} − V_{T N L} ) + V_{T N D} \left( 1 + \sqrt{\frac{K_{n D}}{K_{nL}}} \right)}{1 + \sqrt{\frac{K_{n D}}{K_{nL}}}}$
Noting that
$\sqrt{\frac{K_{n D}}{K_{nL}}} = \sqrt{\frac{(W/L)_{D}}{(W/L)_{L}}} = 10$

we find
$v_{G S Dt} = \frac{(5 − 1) + (1)(1 + 10)}{1 + 10} = 1.36 V$
and
$v_{Ot} = v_{DS Dt} = v_{G S Dt} − V_{T N D} = 1.36 − 1 = 0.36 V$
Considering the transfer characteristics shown in Figure 4.41, we see that the center of the saturation region is halfway between the cutoff point $(v_{G S D} = V_{T N D} = 1 V)$ and the transition point $(v_{G Sdt} = 1.36 V)$, or

$V_{G S Q} = \frac{1.36 − 1.0}{2} + 1.0 = 1.18 V$
Also
$V_{DS D Q} = \frac{4 − 0.36}{2} + 0.36 = 2.18 V$
Trade-offs: Considering the tolerances in the $k´_{n}$ parameter, we find the range in the small-signal voltage gain to be
$|A_{v}|_{max} = \sqrt{\frac{k´_{n D}}{k´_{nL}} \cdot \frac{(W/L)_{D}}{(W/L)_{L}}} = \sqrt{\frac{1.05}{0.95} \cdot (100)} = 10.5$
and
$|A_{v}|_{min} = \sqrt{\frac{k´_{n D}}{k´_{nL}} \cdot \frac{(W/L)_{D}}{(W/L)_{L}}} = \sqrt{\frac{0.95}{1.05} \cdot (100)} = 9.51$

The tolerances in the $k´_{n}$ and $V_{T N}$ parameters will also affect the Q-point. This analysis is left as an end-of-chapter problem.
Comment: These results show that a very large difference is required in the sizes of the two transistors to produce a gain of 10. In fact, a gain of 10 is about the largest practical gain that can be produced by an  enhancement load device. A larger small-signal gain can be obtained by using a depletion-mode MOSFET as a load device, as shown in the next section.
Design Pointer: The body effect of the load transistor was neglected in this analysis. The body effect will actually lower the small-signal voltage gain from that determined in the example