Objective: Design an NMOS inverter to meet a set of specifications and determine the power dissipation in the inverter. Specifications: The NMOS inverter with depletion load shown in Figure 16.7(a) is to be designed such that vO = VO L = 0.10 V when vI = 2.5 V. The circuit is biased at VDD = 2.5 V

Question

Objective: Design an NMOS inverter to meet a set of specifications and determine the power dissipation in the inverter.

Specifications: The NMOS inverter with depletion load shown in Figure 16.7(a) is to be designed such that [latex]v_{O} = V_{O L} = 0.10 V[/latex] when [latex]v_{I} = 2.5 V[/latex]. The circuit is biased at [latex]V_{DD} = 2.5 V[/latex] (Neglect the body effect.)
Choices: Transistors are available with process conduction parameters of [latex]k´_{n} = 100 µA/V^{2} [/latex] . The driver transistor threshold voltage is [latex]V_{T N D} = 0.5 V[/latex] and the load transistor threshold voltage is [latex]V_{T N L} = −1 V[/latex].

Accepted Answer

For [latex]v_{I} = 2.5 V[/latex], the driver transistor is biased in the nonsaturation region and the load transistor is biased in the saturation region. Using Equation (16.27(b), we find

[latex]\frac{K_{D}}{K_{L}} [2(v_{I} − V_{T N D})v_{O} − v^{2}_{O}] = (−V_{T N L})^{2} [/latex] (16.27(b))

[latex]K_{D}[2(2.5 − 0.5)(0.1) − (0.1)^{2} ] = K_{L} [0 − (−1)]^{2} [/latex]
which yields
[latex]\frac{K_{D}}{K_{L}} = 2.56 [/latex]
If we choose [latex](W/L)_{L} = 1[/latex], then
[latex]\frac{K_{D}}{K_{L}} = \frac{(W/L)_{D}}{(W/L)_{L}} ⇒ 2.56 = \frac{(W/L)_{D}}{1} ⇒ \left(\frac{W}{L} \right)_{D} = 2.56 [/latex]

The maximum current in the inverter occurs when the output is in its low state, so, from the load transistor, we find
[latex]i_{D,max} = \frac{k´_{n}}{2} \cdot \left(\frac{W}{L} \right)_{L} (0 − V_{T N L})^{2} = \left(\frac{100}{2} \right) (1)[0 − (−1)]^{2} = 50 µA[/latex]
The maximum power dissipation in the inverter is
[latex]P_{D,max} = i_{D,max} \cdot V_{DD} = (50)(2.5) = 125 µW[/latex]
Comment: A relatively low output voltage [latex]V_{O L}[/latex] can be produced in the NMOS inverter with depletion load, even when the load and driver transistors are not vastly different in size. The power dissipation in this inverter is also substantially less than in the enhancement-load inverter since the aspect ratio is smaller.
Design Consideration: The static analysis of the three types of NMOS inverters clearly demonstrates the advantage of the depletion load inverter. The size of the driver transistor is smaller for a given load device size to produce a given low output state. This allows a greater number of inverters to be fabricated in a given chip area.
In addition, since the power dissipation is less, more inverters can be fabricated on a chip for a given total power dissipation.

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