Objective: Design the bias of a MOSFET circuit such that the Q-point is in the middle of the saturation region. Determine the resulting small-signal voltage gain. Specifications: The circuit to be designed has the configuration shown in Figure 4.17. Let R1||R2 = 100 kΩ. Design the circuit such that

Question

Objective: Design the bias of a MOSFET circuit such that the Q-point is in the middle of the saturation region. Determine the resulting small-signal voltage gain.

Specifications: The circuit to be designed has the configuration shown in Figure 4.17. Let [latex]R_{1}||R_{2} = 100 kΩ[/latex]. Design the circuit such that the Q-point is [latex]I_{DQ} = 2 mA[/latex] and the Q-point is in the middle of the saturation region.

Choices: A transistor with nominal parameters [latex]V_{T N} = 1 V, k´_{n} = 80 µA/V^{2} , W/L = 25[/latex], and [latex]λ = 0.015 V^{−1}[/latex] is available.

Accepted Answer

(dc design): The load line and the desired Q-point are given in Figure 4.18. If the Q-point is to be in the middle of the saturation region, the current at the transition point must be 4 mA.
The conductivity parameter is
[latex]K_{n} = \frac{k´_{n}}{2} \cdot \frac{W}{L} = \left(\frac{0.080}{2} \right) (25) = 1 mA/V^{2}[/latex]

We can now calculate [latex]V_{DS} (sat)[/latex] at the transition point. The subscript t indicates transition point values. To determine [latex]V_{GSt}[/latex] , we use
[latex]I_{Dt} = 4 = K_{n}(V_{GSt} − V_{T N} )^{2} = 1(V_{GSt} − 1)^{2}[/latex]
which yields
[latex]V_{GSt} = 3 V[/latex]
Therefore
[latex]V_{DSt} = V_{GSt} − V_{T N} = 3 − 1 = 2 V[/latex]
If the Q-point is in the middle of the saturation region, then [latex]V_{DSQ} = 7 V[/latex], which would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 4.17, we can write
[latex]V_{DSQ} = V_{DD} − I_{DQ} R_{D}[/latex]
or
[latex]R_{D} = \frac{V_{DD} − V_{DSQ}}{I_{DQ}} = \frac{12 − 7}{2} = 2.5 k\Omega[/latex]
We can determine the required quiescent gate-to-source voltage from the current equation, as follows:
[latex]I_{DQ} = 2 = K_{n}(V_{GSQ} − V_{T N} )^{2} = (1)(V_{GSQ} − 1)^{2}[/latex]
or
[latex]V_{GSQ} = 2.41 V[/latex]
Then
[latex]V_{GSQ} = 2.41 = \left(\frac{R_{2}}{R_{1} + R_{2}} \right) (V_{DD}) = \left(\frac{1}{R_{1}} \right) \left( \frac{R_{1} R_{2}}{R_{1} + R_{2}} \right) (V_{DD}) [/latex]

[latex]= \frac{R_{i}}{R_{1}} \cdot V_{DD} = \frac{(100)(12)}{R_{1}} [/latex]
which yields
[latex]R_{1} = 498 k \Omega[/latex] and [latex]R_{2} = 125 k\Omega[/latex]

(ac analysis): The small-signal transistor parameters are
[latex]g_{m} = 2 \sqrt{K_{n} I_{D Q}} = 2\sqrt{(1)(2)} = 2.83 mA/V[/latex]
and
[latex]r_{o} = \frac{1}{λ I_{D Q}} = \frac{1}{(0.015)(2)} = 33.3 k\Omega[/latex]
The small-signal equivalent circuit is the same as shown in Figure 4.7. The small-signal voltage gain is
[latex]A_{v} = \frac{V_{o}}{V_{i}} = −g_{m} (r_{o} || R_{D} ) = −(2.83)(33.3||2.5)[/latex]
or
[latex]A_{v} = −6.58 [/latex]
Comment: Establishing the Q-point in the middle of the saturation region allows the maximum symmetrical swing in the output voltage, while keeping the transistor biased in the saturation region

Q. 4.4

Chapter 4

Q. 4.4

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