## Chapter 3

## Q. 3.17

Objective: Design the biasing of a multistage MOSFET circuit to meet specific requirements.

Consider the circuit shown in Figure 3.52 with transistor parameters K_{n1} = 500 µA/V² , K_{n2} = 200 µA/V² , V_{T N1} = V_{T N2} = 1.2 V, and λ_{1} = λ_{2} = 0. Design the circuit such that I_{DQ1} = 0.2 mA, I_{DQ2} = 0.5 mA, V_{DSQ1} = V_{DSQ2} = 6 V, and R_{i} = 100 k\Omega. Let R_{Si} = 4 k \Omega.

## Step-by-Step

## Verified Solution

For output transistor M_{2}, we have

V_{DSQ2} = 5 − (−5) − I_{DQ2} R_{S2}

or

6 = 10 − (0.5) R_{S2}

which yields R_{S2} = 8 k \Omega. Also, assuming transistors are biased in the saturation region,

I_{DQ2} = K_{n2}(K_{GS2} − V_{T N2})^{2}

or

0.5 = 0.2(V_{GS2} − 1.2)^{2}

which yields

V_{GS2} = 2.78 V

Since V_{DSQ2} = 6 V, the source voltage of M_{2} is V_{S2} = −1 V. With V_{GS2} = 2.78 V, the gate voltage on M_{2} must be

V_{G2} = −1 + 2.78 = 1.78 V

The resistor R_{D1} is then

R_{D1} = \frac{5 − 1.78}{0.2} = 16.1 k \Omega

For V_{DSQ1} = 6 V, the source voltage of M_{1} is

V_{S1} = 1.78 − 6 = −4.22 V

The resistor R_{S1} is then

R_{S1} = \frac{−4.22 − (−5)}{0.2} = 3.9 k \Omega

For transistor M_{1}, we have

I_{DQ1} = K_{n1}(V_{GS1} − V_{T N1})^{2}

or

0.2 = 0.50(V_{GS1} − 1.2)^{2}

which yields

V_{GS1} = 1.83 V

To find R_{1} and R_{2}, we can write

V_{GS1} =\left(\frac{R_{2}}{R_{1} + R_{2}} \right) (10) − I_{DQ1} R_{S1}

Since

\frac{R_{2}}{R_{1} + R_{2}} = \frac{1}{R_{1}} \cdot \left(\frac{R_{1} R_{2}}{R_{1} + R_{2}} \right) = \frac{1}{R_{1}} \cdot R_{i}

then, since the input resistance is specified to be 100 kΩ, we have

1.83 = \frac{1}{R_{1}} (100)(10) − (0.2)(3.9)

which yields R_{1} = 383 kΩ. From R_{i} = 100 k \Omega, we find that R_{2} = 135 k \Omega.

Comment: Both transistors are biased in the saturation region, as assumed, which is desired for linear amplifiers as we will see in the next chapter.