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## Q. 16.7

Objective: Determine the critical voltages on the voltage transfer curve of a CMOS inverter.

Consider a CMOS inverter biased at $V_{DD} = 5 V$ with transistor parameters $K_{n} = K_{p}$ and $V_{T N} = −V_{T P} = 0.8 V$. Then consider another CMOS inverter biased at $V_{DD} = 3 V$ with transistor parameters $K_{n} = K_{p}$ and $V_{T N} = – V_{T P} = 0.6 V$

## Verified Solution

$(V_{DD} = 5 V)$: The input voltage at the transition points is, from Equation (16.41),

$v_{I} = v_{I t} = \frac{V_{DD} + V_{T P} + \sqrt{\frac{K_{n}}{K_{p}}} V_{T N}}{1 + \sqrt{\frac{K_{n}}{K_{p}}}}$               (16.41)

$V_{I t} = \frac{5 + (−0.8) + \sqrt{1}(0.8)}{1 + \sqrt{1}} = 2.5 V$
The output voltage at the transition point for the PMOS is, from Equation (16.37(b)),
$V_{O Pt} = V_{I t} − V_{T P} = 2.5 − (−0.8) = 3.2 V$
and the output voltage at the transition point or the NMOS is, from Equation (16.38(b)),
$V_{O Nt} = V_{I t} − V_{T N} = 2.5 − 0.8 = 1.7 V$

$(V_{DD} = 3 V)$: The critical voltages are
$V_{I t} = 1.5 V V_{O Pt} = 2.1 V V_{O Nt} = 0.9 V$

Comment: The two voltage transfer curves are shown in Figure 16.27. These figures depict another advantage of CMOS technology, that is CMOS circuits can be biased over a relatively wide range of voltages.