# Question 16.14: Objective: Determine the currents, voltages, and power dissi...

Objective: Determine the currents, voltages, and power dissipation in two NMOS SRAM cells. The first design uses a depletion-load device and the second design uses a resistor-load device.

Assume the following parameters: $V_{DD} = 3 V$ and $k´_{n} = 60 µA/V²$ ; driver transistors: $V_{T N D} = 0.5 V$ and $(W/L)_{D} = 2$; load devices:  $V_{T N L} = −1.0 V, (W/L)_{L} = 1/2$, and R = 2 MΩ.

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Question: 16.2

## Objective: Design an NMOS inverter to meet a set of specifications and determine the power dissipation in the inverter. Specifications: The NMOS inverter with saturated load shown in Figure 16.5(a) is to be designed such that vO = 0.1 V when vI = 2.0 V. The circuit is biased at VDD = 2.5 V. ...

The maximum output voltage (defined as a logic 1),...
Question: 16.3

## Objective: Design an NMOS inverter to meet a set of specifications and determine the power dissipation in the inverter. Specifications: The NMOS inverter with depletion load shown in Figure 16.7(a) is to be designed such that vO = VO L = 0.10 V when vI = 2.5 V. The circuit is biased at VDD = 2.5 V ...

For $v_{I} = 2.5 V$, the driver tran...
Question: 16.11

## Objective: Design a CMOS logic circuit to implement a particular logic function. Implement the logic function Y = AB + C(D + E) in a CMOS design. The signals A, B, C, D, and E are available. Design Approach: The general CMOS design is shown in Figure 16.38, in which the inputs are applied to both ...

(NMOS Design): In the overall function, we note th...
Question: 16.8

## Objective: Calculate the power dissipation in a CMOS inverter. Consider a CMOS inverter with a load capacitance of CL = 2 pF biased at VDD = 5 V. The inverter switches at a frequency of f = 100 kHz. ...

From Equation (16.52), power dissipation in the CM...
Question: 16.7

## Objective: Determine the critical voltages on the voltage transfer curve of a CMOS inverter. Consider a CMOS inverter biased at VDD = 5 V with transistor parameters Kn = Kp and VT N = −VT P = 0.8 V. Then consider another CMOS inverter biased at VDD = 3 V with transistor parameters Kn = Kp and VT N ...

$(V_{DD} = 5 V)$: The input voltage ...
Question: 16.6

## Objective: Determine the low output voltage of an NMOS NAND circuit. Consider the NAND logic circuit shown in Figure 16.13 biased at VDD = 2.5 V. Assume transistor parameters of k´n = 100 µA/V² , VT N D = 0.4 V, VT N L = −0.6 V, (W/L)D = 8, and (W/L)L = 1. Neglect the body effect. ...

If either A or B is a logic 0, then v_{O}[/...
Question: 16.5

## Objective: Determine the low output voltage of an NMOS NOR circuit. Consider the NOR logic circuit in Figure 16.12 biased at VDD = 2.5 V. Assume transistor parameters of k´ n = 100 µA/V² , VT N D = 0.4 V, VT N L = −0.6 V, (W/L)D = 4, and (W/L)L = 1. Neglect the body effect. ...

If, for example, A = logic 1 = 2.5 V and B = logic...
Question: 16.4

## Objective: Determine the change in the high output voltage of an NMOS inverter with enhancement load, taking the body effect into account. Consider the NMOS inverter with enhancement load in Figure 16.9(a). The transistor parameters are VT N DO = VT N LO = 0.5 V and K D/KL = 16. Assume the inverter ...

When $v_{I} \lt V_{T N DO}$ , the dri...
Question: 16.1