Objective: Determine the currents, voltages, and power dissipation in two NMOS SRAM cells. The first design uses a depletion-load device and the second design uses a resistor-load device.

Assume the following parameters: $V_{DD} = 3 V$ and $k´_{n} = 60 µA/V²$ ; driver transistors: $V_{T N D} = 0.5 V$ and $(W/L)_{D} = 2$ ; load devices: $V_{T N L} = −1.0 V, (W/L)_{L} = 1/2$ , and R = 2 MΩ.

Question

Objective: Determine the currents, voltages, and power dissipation in two NMOS SRAM cells. The first design uses a depletion-load device and the second design uses a resistor-load device.

Assume the following parameters: [latex]V_{DD} = 3 V[/latex] and [latex]k´_{n} = 60 µA/V²[/latex] ; driver transistors: [latex]V_{T N D} = 0.5 V[/latex] and [latex](W/L)_{D} = 2[/latex]; load devices: [latex]V_{T N L} = −1.0 V, (W/L)_{L} = 1/2[/latex], and R = 2 MΩ.

Accepted Answer

(With Depletion Load): Assume [latex]M_{2}[/latex] is cut off in the circuit in Figure 16.74(a)
so that [latex]\bar{Q} = V_{DD} = 3 V[/latex]. [latex]M_{1}[/latex] is on in the nonsaturation region and [latex]M_{3}[/latex] is on in the saturation region. The drain current in [latex]M_{1}[/latex] and [latex]M_{3}[/latex] is then
[latex]i_{D} = \frac{k´_{n}}{2} \cdot \left(\frac{W}{L} \right)_{L} (V_{GSL} − V_{T N L})^{2} = \frac{60}{2} \cdot \left(\frac{1}{2} \right) (0 − (−1))^{2}[/latex]
or
[latex]i_{D} = 15 µA[/latex]
The power dissipated in the circuit is then
[latex]P = i_{D} \cdot V_{DD} = (15)(3) = 45 µW[/latex]
The logic 0 value of the Q output is found from
[latex]i_{D} = \frac{k´_{n}}{2} \cdot \left(\frac{W}{L} \right)_{D} [(V_{GSD} − V_{T N D}) V_{DSD} − V^{2}_{DSD} ][/latex]

or
[latex]15 = \frac{60}{2} \cdot (2)[2(3 − 0.5)Q − Q^{2} ] [/latex]
which yields
Q = 50.5 mV

(With Resistor Load): Again assume [latex]M_{2}[/latex] is cut off in the circuit in Figure 16.74(b) so that [latex]\bar{Q} = V_{DD} = 3 V[/latex]. Again [latex]M_{1}[/latex] is on in the nonsaturation region. The drain current is found from
[latex]\frac{V_{DD} − Q}{R} = \frac{k´_{n}}{2} \cdot \left(\frac{W}{L} \right)_{D} [2 (V_{GSD} − V_{T N D}) Q − Q^{2} ] [/latex]
or
[latex]\frac{3 − Q}{2} = \frac{60}{2} \cdot (2)[2(3 − 0.5) Q − Q^{2} ] [/latex]
[Note that dividing by megohms on the left agrees with microamperes on the right.]
We find
[latex]Q \cong 5 mV[/latex]
The drain current is then found:
[latex]i_{D} = \frac{V_{DD} − Q}{R} = \frac{3 − 0.005}{2} \cong 1.5 µA[/latex]
The power dissipated in the circuit is then
[latex]P = i_{D} \cdot V_{DD} = (1.5)(3) = 4.5 µW[/latex]
Comment: We see that the SRAM with the resistive load dissipates 10 times less power than the SRAM with the depletion-load device. Thus, for a given allowed power dissipation per chip, the memory with the resistive load could be 10 times larger than that using the depletion load device.

Question 16.14: Objective: Determine the currents, voltages, and power dissi...

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