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## Q. 16.6

Objective: Determine the low output voltage of an NMOS NAND circuit. Consider the NAND logic circuit shown in Figure 16.13 biased at $V_{DD} = 2.5 V$. Assume transistor parameters of $k´_{n} = 100 µA/V² , V_{T N D} = 0.4 V, V_{T N L} = −0.6 V, (W/L)_{D} = 8$, and $(W/L)_{L} = 1$. Neglect the body effect.

## Verified Solution

If either A or B is a logic 0, then $v_{O}$ = logic 1 = 2.5 V.
If A = B = logic 1 = 2.5 V, then both driver transistors are driven in the nonsaturation region and the output goes low. As a good approximation, we will assume the effective length of the driver transistor doubles. Then, using Equation (16.27(b)), we have

$\frac{K_{D}}{K_{L}} [2(v_{I} − V_{T N D})v_{O} − v^{2}_{O} ] = (−V_{T N L})^{2}$           (16.27(b))

$\frac{\frac{1}{2} \cdot \left(\frac{W}{L} \right)_{D}}{\left(\frac{W}{L} \right)_{L}} [2(v_{I} − V_{T N D})v_{O} − v^{2}_{O} ] = (−V_{T N L})^{2}$
or
$\frac{8}{(2)(1)} [2(2.5 − 0.4)v_{O} − v^{2}_{O} ] = [−(−0.6)]^{2}$
The output voltage is found to be $v_{O} = 21.5 mV$.
This output voltage is the same value that would be obtained for a simple inverter with $(W/L)_{D} = 4$, and $(W/L)_{L} = 1$.
Comment: If an N-input NMOS NAND logic gate were to be fabricated then the width-to-length ratio of the drivers would need to be N times that of a single driver in an NMOS inverter to achieve a given value of $V_{O L}$ . The increase in the required area of the driver transistors in a NAND logic gate means that logic gates with more than three or four inputs are not attractive.