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## Q. 16.5

Objective: Determine the low output voltage of an NMOS NOR circuit.

Consider the NOR logic circuit in Figure 16.12 biased at $V_{DD} = 2.5 V$. Assume transistor parameters of $k´_{n} = 100 µA/V² , V_{T N D} = 0.4 V, V_{T N L} = −0.6 V, (W/L)_{D} = 4$, and $(W/L)_{L} = 1$. Neglect the body effect

## Verified Solution

If, for example, A = logic 1 = 2.5 V and B = logic 0, then $M_{D A}$ is biased in the nonsaturation region and $M_{DB}$ is cut off. The output voltage is determined from Equation (16.27(b)), which is
$\frac{K_{D}}{K_{L}} [2(v_{I} − V_{T N D})v_{O} − v^{2}_{O}] = (−V_{T N L})^{2}$
or
$\frac{4}{1} [2(2.5 − 0.4)v_{O} − v^{2}_{O} = [−(−0.6)]^{2}$
The output voltage is found to be $v_{O} = 21.5 mV$.
If both inputs go high, then A = B = logic $1 = V_{DD} = 2.5 V$ and the output voltage can be found using Equation (16.29), which is
$(−V_{T N L})^{2} = 2 \left(\frac{K_{D}}{K_{L}} \right) [2(V_{DD} − V_{T N D})v_{O} − v^{2}_{O} ]$

or

$[−(−0.6)]^{2} = 2 \left(\frac{4}{1} \right) [2(2.5 − 0.4)v_{O} − v^{2}_{O} ]$

The output voltage is found to be $v_{O} = 10.7 mV$.

Comment: An NMOS NOR gate must be designed to achieve a specified $V_{O L}$ output voltage when only one input is high. This will give the largest logic 0 value.
When more than one input is high, the output voltage is smaller than the specified $V_{O L}$ value, since the effective width-to-length ratio of the composite driver transistor increases.