Products
Rewards 
from HOLOOLY

We are determined to provide the latest solutions related to all subjects FREE of charge!

Please sign up to our reward program to support us in return and take advantage of the incredible listed offers.

Enjoy Limited offers, deals & Discounts by signing up to Holooly Rewards Program

HOLOOLY 
BUSINESS MANAGER

Advertise your business, and reach millions of students around the world.

HOLOOLY 
TABLES

All the data tables that you may search for.

HOLOOLY 
ARABIA

For Arabic Users, find a teacher/tutor in your City or country in the Middle East.

HOLOOLY 
TEXTBOOKS

Find the Source, Textbook, Solution Manual that you are looking for in 1 click.

HOLOOLY 
HELP DESK

Need Help? We got you covered.

Chapter 5

Q. 5.6

65nm CMOS chain scaling

Consider a 6-stage CMOS amplifier chain where each stage has minimum gate length transistors, with W=20 \mu \mathrm{m} and 20 unit fingers, each 1 \mu \mathrm{m} wide and contacted on both sides of the gate. R_{D}=200 \Omega. Each stage is biased at 0.15 \mathrm{~mA} / \mu \mathrm{m} and the corresponding small signal parameters of the MOSFET are R_{g}=10 \Omega,\left(200 \Omega / N_{f}\right) C_{g s}^{\prime}=0.7 \mathrm{fF} / \mu \mathrm{m}, C_{s b}^{\prime}=C_{d b}^{\prime}=0.7 \mathrm{fF} / \mu \mathrm{m}, C_{g d}^{\prime}=0.4 \mathrm{fF} / \mu \mathrm{m}, g^{\prime}{ }_{m e f f}=0.9 \mathrm{mS} / \mu \mathrm{m}, g_{\text {oeff }}^{\prime}=0.18 \mathrm{mS} / \mu \mathrm{m}. (a) Calculate the DC gain, the 3 \mathrm{~dB} bandwidth and the gain-bandwidth product of the individual stage and of the amplifier chain. (b) Re-design the amplifier chain using size and bias scaling by a factor of 2 from the input to output, knowing that the first stage has R_{D}=62.5 \Omegaand W=64 \mu \mathrm{m}. Assume the same bias current density, and small signal parameters per unit gate width as in the original amplifier.

Step-by-Step

Verified Solution

The low-frequency voltage gain per stage is

A_{S}=-g_{\text {meff }}\left(r_{o}|| R_{D}\right)=-0.9 e-3 \times 20 \times 116=-2.088 \\

 

\tau_{p}=\left(R_{D} \| r_{o}\right)\left[C_{d b}+C_{g s}+\left(2+\left|A_{0}\right|\right) C_{g d}\right]+R_{g}\left[C_{g s}+\left(1+\left|A_{0}\right|\right) C_{g d}\right]=7.55 p s \\

 

B W_{S}=\frac{1}{2 \pi \tau_{p}}=21.1 G H z

 

G B W_{S}=44.05 \mathrm{GHz}

For the chain, A_{t o t}=2.088^{6}=82.86=38.36 \mathrm{~dB}, B W_{t o t}=\left(\sqrt{2^{1 / 6}-1}\right) 21.1 e 9=7.38 \mathrm{GHz} and G B W_{\text {tot }}=632.9 \mathrm{GHz}.

An exact computer simulation using the design kit models gives A_{S}=6.4 \mathrm{~dB}(2.089), B W_{s}=18.96 \mathrm{GHz}, and A_{\text {tot }}=38.37 \mathrm{~dB}, B W_{\text {tot }}=6.2 \mathrm{GHz}. The error between the hand calculations and exact simulation is 10 % for the stage and about 16 % for the entire chain.
(b) If we use scaling by  k=2 : W_{1}=64 \mu \mathrm{m} , R_{D 1}=62.5 \Omega , W_{2}=32 \mu \mathrm{m}, R_{D 2}=125 \Omega, . . . , W_{6}=2 \mu \mathrm{m} , R_{D 6}=2 \mathrm{k} \Omega

The gain per stage remains unchanged, but the time constant and bandwidth of the stage change to

\tau_{p} =\left(R_{D} \| r_{\mathrm{o}}\right)\left[C_{g d}+C_{d b}+\frac{C_{g s}}{k}+\left(1+\left|A_{0}\right|\right) \frac{C_{g d}}{k}\right]+R_{g}\left[C_{g s}+\left(1+\left|A_{0}\right|\right) C_{g d}\right]\

 

=36.25[25.6 \mathrm{f}+44.8 \mathrm{f}+22.4 \mathrm{f}+3.1 \times 12.8 \mathrm{f}]+3.125[44.8 \mathrm{f}+3.1 \times 25.6 \mathrm{f}] \\

 

=4.9 \mathrm{ps}+0.388 \mathrm{ps}=5.288 \mathrm{ps}

We obtain B W_{S}^{\prime}=30.1 \mathrm{GHz}, almost a 50 % increase in stage bandwidth compared to the original amplifier, and B W_{t o t}^{\prime}=\left(\sqrt{2^{1 / 6}-1}\right) 30.1 e 9=10.53 \mathrm{GHz}.

Using computer simulation, we obtain B W^{\prime}_{S}=28.17 \mathrm{GHz},B W_{\text {tot }}^{\prime}=8.73 \mathrm{GHz},G B W^{\prime}{ }_{S}=59.15 \mathrm{GHz},G B W_{\text {tot }}^{\prime}=748.7 \mathrm{GHz}

Again, the error between hand calculations and computer simulations using design kit models is within 10 % for the single stage but increases to 17.1 % for the entire chain.

Note that, if we consider interconnect capacitance and the parasitic capacitance of the load resistor, the calculated bandwidth will be smaller because the interconnect capacitance is comparable to that of the smallest size stage.