(a) For the lumped stage, biasing each transistor at 0.15 \mathrm{~mA} / \mu \mathrm{m} , g_{m e f f}=162 \mathrm{mS} , r_{o e f f}=30.86 \Omega,  A_{S}=-0.162 \times 13.81=-2.23
We assume that this stage is in a chain of identical stages
\tau_{p}=\left(R_{D} \| r_{o}\right)\left[C_{d b}+C_{g s}+\left(2+\left|A_{0}\right|\right) C_{g d}\right]+R_{g}\left[C_{g s}+\left(1+\left|A_{0}\right|\right) C_{g d}\right]
=(25|| 30.86) \times 556.56 \mathrm{f}+1.11 \times 358.6 \mathrm{f}=8.073 \mathrm{ps} \\
B W_{S}=\frac{1}{2 \pi \tau_{p}}=19.72 \mathrm{GHz}

(b) In the distributed amplifier case: W=36 \mathrm{um}, 5 stages. Again, each transistor is biased at 0.15 \mathrm{~mA} / \mu \mathrm{m} . The total current is 26 \mathrm{~mA}, W_{\text {total }}=180 \mu \mathrm{m} . V_{D D}=1.2 \mathrm{~V}

The calculated input capacitance per stage is (3.23 \times 0.4 \mathrm{f}+0.7 \mathrm{f}) \times 36=71.76 \mathrm{fF}.
To match the input line to \mathrm{Z}_{0}=50 \Omega, \mathrm{L}_{\text {gate }}=179 \mathrm{pH} (from L=C Z_{0}^{2} ) and results in a line cutoff frequency of 88.76 \mathrm{GHz}. To match the output line impedance and delay to that of the input, we add 0.55 \mathrm{fF} \times 36=19.8 \mathrm{fF} at the drain of each stage and select the same inductance value L_{D}=179 \mathrm{pH}. We obtain in simulation A_{S}=6.9-7.3 \mathrm{~dB} (ripple), B W_{S}=73 \mathrm{GHz}, 3.7 times larger than that of the lumped stage.