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## Q. 1.1.3

The block diagram of a frequency synthesizer consisting of a phase locked loop (PLL) and divided by N counter (comprising ÷2, ÷4, ÷8, ÷16 outputs) is sketched below. the synthesizer is excited with a 5 kHz signal (input 1). The free running frequency of the PLL is set to 20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1 – 2 – 3 – 4.The corresponding frequencies synthesized are

(A) 10 kHz, 20 kHz, 40 kHz, 80 kHz

(B) 20 kHz, 30 kHz, 80 kHz, 160 kHz

(C) 80 kHz, 40 kHz, 20 kHz, 10 kHz

(D) 160 kHz, 80 kHz, 40 kHz, 20 kHz

## Verified Solution

Running freq is set to be 20 kHz. Here freq divider is used with N counter. O/p freq becomes N times the given freq so the outputs are 2 × 5 = 10 Hz, 4 × 5 = 20 Hz, 8 × 5 = 40 Hz, 16 × 5 = 80 Hz
Hence, the correct option is (A).