Microelectronic Circuits 7th. Edition by Adel S. Sedra, Kenneth C. Smith | 9780199339136 | 0199339139 | Holooly

Microelectronic Circuits

136 SOLVED PROBLEMS

Question: 14.6

Determining the Propagation Delay of the CMOS Inverter For the 0.25-μm process characterized by VDD = 2.5 V, Vtn = −Vtp = 0.5 V, k′n = 3.5 k′ p = 110 μA/V², find tPLH, tPHL, and tP for an inverter for which (W/L)n = 1.5 and (W/L)p = 3, and for C = 10 fF. Use both the approach based on average ...

Question: 14.5

Calculating the Propagation Delay of a Simple Inverter Return to the inverter of Fig. 14.17(a) and consider the case where a capacitor C is connected between the output node and ground. If at t = 0, vI goes low, and assuming that the switch opens instantaneously, find the time for vO to reach 1/2 ...

Question: 16.1

The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μm process for which μnCox = 4 μpCox = 300 μA/V², Vtn = |Vtp| = 0.5 V, and VDD = 1.8 V. The inverters have (W/L)n = 0.27 μm/0.18 μm and (W/L)p = 4(W/L)n. The four NMOS transistors in the set–reset circuit have equal W/L ratios.(a) Determine ...

Question: 15.2

Consider a pseudo-NMOS inverter fabricated in a 0.25-μm CMOS technology for which μnCox = 115 μA/V², μpCox = 30 μA/V², Vtn = −Vtp = 0.5 V, and VDD = 2.5 V. Let the W/L ratio of QP be (0.25 μm/0.25 μm) and r = 9. Find: (a) VOH, VOL, VIL , VIH , VM, NMH, and NML (b) (W/L)n (c) Istat and PD (d) tPLH, ...

Question: 15.1

Consider MOS transistors fabricated in a 0.25-μm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 0.5 V, μnCox = 115 μA/V², μpCox = 30 μA/V², λn = 0.06 V^−1, and |λp| = 0.1 V^−1. Let L = 0.25 μm and (W/L)n = (W/L)p = 1.5. Measurements indicate that for the NMOS transistor, VDSsat = 0.63 V, and for ...

Question: 14.9

Design of an Inverter Chain to Drive a Large Load Capacitance An inverter whose input capacitance C = 10 fF and whose equivalent output resistance R = 1 kΩ must ultimately drive a load capacitance CL = 1 pF. (a) What is the time delay ...

Question: 14.8

Transistor Sizing of a CMOS Gate Provide transistor W/L ratios for the logic circuit shown in Fig. 14.36. Assume that for the basic inverter n = 1.5 and p = 5 and that the channel length is 0.25 μm. ...

Question: 14.7

Determining the Effective Load Capacitance C and the Propagation Delay Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 fF/μm², μnCox = 110 μA/V², ...

Question: 17.3

For the feedback loop of Fig. 17.29, find the sensitivities of ω0 and Q relative to all the passive components and the op-amp gain. Evaluate these sensitivities for the design considered in the preceding section for which C1 = C2. ...

Question: 17.2

Find the Chebyshev transfer function that meets the same low-pass filter specifications given in Example 17.1: namely, fp = 10 kHz, Amax = 1 dB, fs = 15 kHz, Amin = 25 dB, dc gain = 1. ...

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