Question 8.2: Write the source code for a program starting in location $03...
Write the source code for a program starting in location $0300 that loads register A with the signed two’s-complement number in location $0200, computes its absolute value, returns the result to location $0200, clears the A register, and then stops. Use the instructions listed in Table 8.1. (Assume that the initial content of location $0200 is never 10000000 = −128_{10} which does not have a positive equivalent in 8-bit two’s complement form.)
| Table 8.1. Selected Instructions for the CPU12 (Cont.) | |||||||||||
| Source Form |
Operation | Addr. Mode | Machine Code | Condition Codes | |||||||
| S | X | H | I | N | Z | V | C | ||||
| STOP | Stop Internal Clocks. If S control bit = 1, the STOP instruction is disabled and acts like a NOP | INH | 18 3E | – | – | – | – | – | – | – | – |
| TSTA | Test Accumulator A; (A) − 00 | INH | 97 | – | – | – | – | \updownarrow | \updownarrow | 0 | 0 |
| TSTB | Test Accumulator B; (B) − 00 | INH | D7 | – | – | – | – | \updownarrow | \updownarrow | 0 | 0 |
| S indicates instructions that are intended for two’s complement signed numbers U indicates instructions that are intended for unsigned numbers * For indexed addressing (IDX). Only the first byte of the machine coded is given. An additional one to three bytes are needed. The details are beyond the scope of our discussion. ii 8-bit immediate data dd low byte of a direct address hh ll high and low bytes of an extended address jj kk high and low bytes of 16-bit immediate data rr signed 8-bit offset in branch instruction |
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Recall that branch instructions (also known as conditional instructions)
allow different sets of instructions to be executed depending on the values of certain bits in the condition code register. For example, in Table 8.1, we see that the branch on plus instruction (BPL) causes a branch if the N bit of the condition code register is clear (i.e., logic 0).
Testing occurs automatically in many instructions. For example, in the load A
instruction LDAA,theNandZbits of the condition code register are set if the value
loaded is negative or zero, respectively.
Our plan is to load the number, compute its two’s complement if it is negative,
store the result, clear the A register, and then stop. Recall that one way to find the two’s complement is to first find the one’s complement and add one. If the number is positive, no calculations are needed.
In this program, the number is first loaded into register A from memory location $0200. If the number is negative (i.e., if the most significant bit is 1), the N bit of the condition-code register is set (logic 1); otherwise, it is not set. If the N bit is zero, the BPL PLUS instruction causes the next instruction executed to be the one starting in the location labeled PLUS. On the other hand, if the N bit is one, the next instruction is the one immediately following the branch instruction. Thus, if the content of the memory location is negative, the two’s complement is computed to change its sign. Then, the result is written to the original location and A is cleared.
The source code is:
| ; SOURCE CODE FOR EXAMPLE 8.2 ; ORG $0300 ;ORIGIN DIRECTIVE LDAA $0200 ;LOAD NUMBER INTO REGISTER A INCA ;ADD ONE TO FORM TWO’S COMPLEMENT |