Question 7.18: In the circuit of Fig. 7.67(a), determine the response v(t)....

1. Define. The problem is clearly stated and the circuit is clearly labeled.
2. Present. Given the circuit shown in Fig. 7.67(a), determine the response v(t) .
3. Alternative. We can solve this circuit using circuit analysis techniques, nodal analysis, mesh analysis, or PSpice. Let us solve the problem using circuit analysis techniques (this time Thevenin equivalent circuits) and then check the answer using two methods of PSpice.
4. Attempt. For time < 0  the switch on the left is open and the switch on the right is closed. Assume that the switch on the right has been closed long enough for the circuit to reach steady state; then the capacitor acts like an open circuit and the current from the 4-A source flows through the parallel combination of the 6-Ω  and  3-Ω  resistors (6 \parallel 3 = 18/9 = 2) ,producing a voltage equal to 2 × 4 = 8 V = -v(0) .
At  t = 0 ,the switch on the left closes and the switch on the right opens, producing the circuit shown in Fig. 7.67(b). The easiest way to complete the solution is to find the Thevenin equivalent circuit as seen by the capacitor. The opencircuit voltage (with the capacitor removed) is equal to the voltage drop across the 6-Ω  resistor on the left, or 10 V (the voltage drops uniformly across the 12-Ω resistor, 20 V, and across the 6-Ω  resistor, 10 V). This is V_{Th}   The resistance looking in where the capacitor was is equal to 12 \parallel 6 + 6 = 72/18 + 6 = 10 Ω,  which is  R_{eq} .This produces the Thevenin equivalent circuit shown in Fig. 7.67(c). Matching up the boundary conditions (v(0) = -8 V and v(∞) = 10 V)  and \tau = RC = 1 ,  we get

v(t) = 10 – 18e^{-t} V

5. Evaluate. There are two ways of solving the problem using PSpice.

■ METHOD 1 One way is to first do the dc PSpice analysis to determine the initial capacitor voltage. The schematic of the revelant circuit is in Fig. 7.68(a). Two pseudocomponent VIEWPOINTs are inserted to measure the voltages at nodes 1 and 2. When the circuit is simulated, we obtain the displayed values in Fig. 7.68(a) as V_{1} = 0V  and  V_{2} = -8 V . Thus, the initial capacitor voltage is v(0) =V_{1} – V_{2} = -8V .    The PSpice transient analysis uses this value along with the schematic in Fig. 7.68(b). Once the circuit in Fig. 7.68(b) is drawn, we insert the capacitor initial voltage as IC = -8 . We select Analysis/Setup/Transient and set Print Step to 0.1 s and Final Step to  4 \tau = 4s. After saving the circuit, we select Analysis/ Simulate to simulate the circuit. In the PSpice A/D window, we select Trace/Add and display V(R2:2) -V(R3:2) OR V(C1:1)-V(C1:2) as the capacitor voltage v(t). The plot of v(t)  is shown in Fig. 7.69. This agrees with the result obtained by hand calculation, v(t) = 10 –  18 e^{-t} V.

■ METHOD 2 We can simulate the circuit in Fig. 7.67 directly, since PSpice can handle the open and closed switches and determine the initial conditions automatically. Using this approach, the schematic is drawn as shown in Fig. 7.70. After drawing the circuit, we select Analysis/Setup/Transient and set Print Step to 0.1 s and Final Step to 4 \tau = 4 s .   We save the circuit, then select Analysis/Simulate to simulate the circuit. In the PSpice A/D window, we select Trace/Add and display V(R2:2) – V(R3:2)  as the capacitor voltage v(t)  The plot of v(t) is the same as that shown in Fig. 7.69.

6. Satisfactory? Clearly, we have found the value of the output response v(t) , as required by the problem statement. Checking does validate that solution. We can present all this as a complete solution to the problem.