Question 23.3: Using the topology seen in Fig. 20.22, design a voltage refe......
Using the topology seen in Fig. 20.22, design a voltage reference with, ideally, zero temperature coefficient. Simulate the design to determine the reference’s sensitivity to changes in temperature and VDD. Comment on the repeatability of the V_{REF} (with process variations from one process run to the next) and methods (and concerns) with trimming V_{REF}. Assume TCR = 0.002 (2,000 ppm/C).
We begin by writing the long-channel equation, Eq. (20.40), for the resistance needed for zero temperature coefficient (ZTC)
R=\frac{2}{\frac{\partial V_{T H N}}{\partial T}\cdot K P_{n}\cdot\frac{W}{L}}\left\lgroup1-\frac{1}{\sqrt{K} }\right\rgroup \cdot \left\lgroup\frac{1}{R}\frac{\partial R}{\partial T} +\frac{1}{KP_n} \cdot \frac{\partial KP_n}{\partial T} \right\rgroup (20.40)
R=\frac{2}{\frac{\partial V_{T H N}}{\partial T}\cdot K P_{n}\cdot\frac{W}{L}}\left\lgroup1-\frac{1}{\sqrt{K} }\right\rgroup \cdot \left\lgroup\frac{1}{R}\frac{\partial R}{\partial T} +\frac{1}{KP_n} \cdot \frac{\partial KP_n}{\partial T} \right\rgroup (23.16)
While this equation won’t directly apply for the design in a short-channel process, we can use it, with simulations, to help point us to the factors that influence the temperature behavior of the reference. Substituting in the appropriate numbers with K = 4, we get
R=\frac{1}{(-0.0006)\cdot K P_{n}\cdot\frac{W}{L}}\cdot \left\lgroup(0.002)-\frac{1.5}{300}\right\rgroup (23.17)
or
R={\frac{5}{K P_{n}\cdot{\frac{W}{L}}}} (23.18)
To move the reference towards a ZTC, let’s set the resistor to nominally 5.5k (the same value we used before, see Fig. 20.22 and the associated discussion) and adjust the widths and lengths of the NMOS devices until the simulations show good temperature behavior (keeping in mind that we must keep the W/L of M2 K times the W/L of M1). The resulting circuit is seen in Fig. 23.13. Simulation results are seen in Fig. 23.14. (Note that the currents and gate-source voltages have nothing to do with the values listed in Table 9.2.) The reference voltage is nominally 500 mV (= VDD/2). The reference, according to simulations, moves 40 mV over a 100 °C temperature change (-400 μV/C or a TC of-800 ppm/C, not that great when compared to the references described later). Further, the reference is fairly insensitive to variations in VDD once VDD gets above 600 mV.
A couple of practical notes are needed at this point. While we’ve used simulations to zero in on a design with decent temperature behavior and a reference voltage at VDD/2, actually fabricating this reference would result in a V_{REF} different from the one seen in Fig. 23.14 (in most fabrication runs). The MOSFET characteristics and the sheet resistance vary with each process run.
To adjust the reference voltage to VDD/2, the resistor must be trimmed using fuses, Fig. 23.15. It can be shown that the temperature behavior doesn’t vary significantly with small changes in V_{REF} when trimming. As seen in Eq. (20.38), lowering the resistor value causes V_{REF} to increase, while increasing the resistor value causes V_{REF} to decrease. The fuses in Fig. 23.15 short across the resistor until they are blown. To trim the resistor, we start blowing the resistors (electrically or with a laser). With each blown fuse we add (nominally) 200 Ω in series with the nominally 4k resistor. If the processes’ sheet resistance increases by 20% (so that the resistors are now 4.8k and 240 Ω), then we only need to blow three fuses (neglecting the change in the MOSFET characteristics) to trim the resistor to 5.5k. If the sheet resistance decreases by 20%, then the resistors are 3.2k and 160 Ω. Fifteen fuses would need to be blown to trim the resistor to 5.5k.
V_{R E F}=V_{G S1}=\frac{2}{R\cdot K P_{n}\cdot\frac{W}{L}}\left\lgroup1-\frac{1}{\sqrt{K}}\right\rgroup +V_{T H N} (20.38)
Finally, it’s important to remember that stability is of great importance when using feedback. As discussed in Sec. 20.1.4, the feedback loop is made stable by adding a capacitance on the output of the added amplifier. The bigger this capacitance, the more stable the reference. We stabilize the reference in Fig. 23.13 with the addition of MCP.
Table 9.2 Typical parameters for analog design using the short-channel CMOS process discussed in this book. These parameters are valid only for the device sizes and currents listed.
Short-channel MOSFET parameters for general analog design
VDD = 1 V and a scale factor of 50 nm {scale = 50e-9)
| Parameter | NMOS | PMOS | Comments |
| Bias current, I_D | 10 \mu A | 10 \mu A | Approximate, see Fig. 9.31 |
| W/L | 50/2 | 100/2 | Selected based on I_D\ \text{and}\ V_{o\nu} |
| Actual W/L | 2.5\mu m/100nm | 5\mu m/100nm | L_{min}\ \text{is}\ 50 nm |
| V_{DS,sat}\ \text{and}\ V_{SD,sat} | 50 mV | 50 mV | However, see Fig. 9.32 and
the associated discussion |
| V_{o\nu n}\ \text{and}\ V_{o\nu p} | 70 mV | 70 mV | |
| V_{GS}\ \text{and}\ V_{SG} | 350 mV | 350 mV | No body effect |
| V_{THN}\ \text{and}\ V_{THP} | 280 mV | 280 mV | Typical |
| \partial V_{THN,P}/\partial T | – 0.6 mV/C° | – 0.6 mV/C° | Change with temperature |
| \nu_{satn}\ \text{and}\ \nu_{satp} | 110\times 10^3\ m/s | 90\times 10^3\ m/s | From the BSIM4 model |
| t_{ox} | 14\ \mathring{A} | 14\ \mathring{A} | Tunnel gate current, 5\ A/cm^2 |
| {C}_{o x}^{\prime}=\varepsilon _{ox}/t_{ox} | 25\ fF/\mu m^2 | 25\ fF/\mu m^2 | {C}_{o x}={C}_{o x}^{\prime}WL\cdot (scale)^2 |
| C_{oxn}\ \text{and}\ C_{oxp} | 6.25fF | 12.5fF | PMOS is two times wider |
| C_{gsn}\ \text{and}\ C_{sgp} | 4.17fF | 8.34fF | C_{gs}=\frac{2}{3}C_{ox} |
| C_{gdn}\ \text{and}\ C_{dgp} | 1.56fF | 3.7fF | C_{gd}=CGDO\cdot W\cdot scale |
| g_{mn}\ \text{and}\ g_{mp} | 150\ \mu A/V | 150\ \mu A/V | At\ I_D=10\ \mu A |
| r_{on}\ \text{and}\ r_{op} | 167\ k\Omega | 333\ k\Omega | Approximate at I_D=10\ \mu A |
| g_{mn}r_{on}\ \text{and}\ g_{mp}r_{op} | 25 V/V | 50 V/V | !!Open circuit gain!! |
| \lambda _n\ \text{and}\ \lambda _p | 0.6\ V^{-1} | 0.3\ V^{-1} | L = 2 |
| f_{Tn}\ \text{and}\ f_{Tp} | 6000 MHz | 3000 MHz | Approximate at L = 2 |
