Using the 6-bit charge-scaling DAC shown in Fig. 29.15, (a) show that the output voltage will be \frac{1}{2}\cdot V_{REF} if (a) D_5D_4D_3D_2D_1D_0 = 100000 and (b) the output will be \frac{1}{64}\cdot V_{REF} if D_5D_4D_3D_2D_1D_0 = 000001.
(a) If D_5 = 1 and the remaining bits are all zero, then the equivalent circuit for the DAC can be represented by Fig. 29.16a. The expression for the output voltage then becomes
\nu_{O U T}=\frac{4}{\left\lgroup\frac{8}{7}\mathrm{~in~series~with~8}\right\rgroup +3+4}\cdot V_{R E F}=\frac{1}{2}\cdot V_{R E F}(b) For the second case, the equivalent circuit can be seen in Fig. 29.16b. The intermediate node voltage, V_A, is simply the voltage division between the C associated with D_0 and the remainder of the circuit, or
V_A=V_{REF}\cdot \frac{1}{\left\lgroup7+\frac{\frac{8}{7}\cdot 7 }{\frac{8}{7}+ 7 } \right\rgroup } =\frac{1}{8+\frac{56}{57} } \cdot V_{REF} (29.36)
The output voltage can be written as
\nu_{O U T}=V_{A}\cdot\frac{\frac{8}{7}}{\frac{8}{7}+7}=\frac{8}{57}\cdot V_{A} (29.37)
Plugging Eq. (29.36) into Eq. (29.37) yields
\nu_{O U T}=V_{R E F}\cdot\frac{8}{(8\cdot57)+56}=\frac{V_{R E F}}{64} (29.38)
which is the desired result.