Question 16.20: Illustrate and discuss the architecture of FPGAs....

FPGAs take the form of a two-dimensional array of logic cells. These may be arranged in rows, or, more commonly in a rectangular grid as shown in Fig. 16.16. The size of the array varies considerably, with small devices having about 64 cells, while larger devices may have more than 1000 cells. Between the cells of the array run groups of vertical and horizontal channels that can be used to route signals through the circuit. Programmable switches are used to interconnect these conductors and so provide point-to-point connections.

The programmable switches within FPGAs may be either one time programmable (OTP) or reprogrammable. OTP parts are based on the use of antifuse rather than the conventional fuses used in PALs.

Reprogrammability is achieved by replacing each antifuse with a transistor switch (a MOSFET). The state of the switch is then determined by a memory element that can be set either to open or to close the switch. You can visualize this memory element as a bistable element. This technique is referred to as a static random access memory (SRAM) approach and has the advantage that the contents of the memory can be changed as often as desired. The device is therefore completely reprogrammable. One disadvantage of this approache is that the content of the memory is volatile, and is lost when the power is removed. To overcome this problem the states of the various interconnections must be loaded from some nonvolatile memory (ROM or computer disk) when power is first applied.

FPGAs are particularly useful when implementing systems that require on-chip memory or that benefit from distributed architecture. Modern FPGAs operate at very high speeds, but are generally not as fast as PALs or CPLDs. Also, their propagation delay times are greatly affected by the route taken by the signals within the chips. This makes it very difficult to predict a circuit’s performance before it is completed. This is in marked contrast to PALs and CPLDs where delay times are totally predictable.