Question 10.6: D Latch Create a D latch using the block design method. Righ......
D Latch
Create a D latch using the block design method. Right-click in the block design area and insert the symbol named latch. Test the design by creating a waveform simulation file. Repeat using the VHDL design entry method.
Figure 10–17 shows the solution as a bdf file using the primitive symbol LATCH. d0 and e0 are applied as inputs and q0 is the output.
The VHDL solution is shown in Figure 10–18. Notice that d0 and e0 are listed in the sensitivity list of the PROCESS statement. This way, whenever either of them changes levels, the process is executed. The IF clause sets q0 equal to d0 when e0 is HIGH. (If e0 is not HIGH, q0 remains unchanged.)
The waveform simulation file is shown in Figure 10–19. This simulation must be run for both design methods (block and VHDL) to check the validity of both implementations. [Follow the procedure outlined in Section 4–4 (Steps 38–40) to assign the bdf file, then the vhd file to the current project before each simulation.] Notice in the simulation that q0 follows the state of d0 while e0 is HIGH, then it becomes latched when e0 goes LOW.
