Finding the effects of offsets on the output of an op-amp integrator The inverting integrator in Fig. 14.7 has R_{1}=1 k \Omega, R_{ X }=1 k \Omega, C_{ F }=0.1 \mu F , V_{ CC }=15 V ,-V_{ EE }=-15 V , and maximum saturation voltage = ±14 V. The op-amp parameters are V_{ io }=6 mV , I_{ B }=500 nA \text {, and } I_{ io }=200 nA \text { at } 25^{\circ} C .
(a) Determine the total output offset voltage v_{ of }.
(b) Repeat part (a) if R_{ x }=0
R_{1}=1 k \Omega, R_{ x }=1 k \Omega, V_{ io }=6 mV , I_{ B }=500 nA , \text { and } I_{ io }=200 nA . The equivalent circuit of the integrator with input offset voltage and input biasing currents is also shown in Fig. 14.7.
(a) R_{ x }=R_{1} . The output voltage will be due to V_{\text {io }} \text { and } I_{\text {io }} \text {. With } V_{\text {io }}=0 , we get
\begin{aligned}&v_{+}=-R_{ X } I_{ B 1}=-R_{1} I_{ B 1} \\&v_{-}=v_{+}=-R_{1} I_{ B 1} \\&i_{ S }=-\frac{v_{-}}{R_{1}} \\&i_{ f }=i_{ S }-I_{ B 2}=I_{ B 1}-I_{ B 2}\end{aligned}
With I_{ B 1}=I_{ B 2}=0, we get
i_{ f }=\frac{-V_{ io }}{R_{1}}
Applying the superposition theorem, we get for the current flowing through the capacitor C _{ F }
i_{ f }=i_{ S }+I_{ B 1}-I_{ B 2}=\frac{-V_{ io }}{R_{1}}+I_{ io } (14.12)
where I_{ io }=\left(I_{ B 1}-I_{ B 2}\right) is the input offset current. The total output offset voltage due to the capacitor current i_{ f } can be found from
-v_{\text {of }}=\frac{1}{C_{ F }} \int i_{ f } d t+\left(-V_{ io }+R_{ x } I_{ B 1}\right)+v_{ C }(t=0) (14.13)
where v_{ C }(t=0) is the initial capacitor voltage. Substituting i_{ f } from Eq. (14.12) into Eq. (14.13) gives the total output offset voltage as
-v_{ of }=\frac{1}{C_{ F }} \int\left(\frac{-V_{ io }}{R_{1}}+I_{ io }\right) d t+\left(-V_{ io }+R_{ x } I_{ B 1}\right)+v_{ C }(t=0)
v_{ of }=\frac{V_{ io }}{C_{ F } R_{1}} t-\frac{I_{ io }}{C_{ F }} t+V_{ io }-R_{ x } I_{ B 1}-v_{ C }(t=0) (14.14)
This equation indicates that the output offset voltage will rise linearly until the output reaches the saturation voltage of the amplifier, which is ±14 V in this example. If the power supplies are turned on and enough time is allowed, the output will build up to the saturation voltage, even without any external input signal to the integrator. For this reason, this is not a practical circuit (as discussed in Sec. 3.5); it needs a DC feedback resistor R _{ F } , as shown in Fig. 3.16. After the power supply is switched on, the time required for the total output offset voltage to reach the saturation level v_{ of }=14 V can be found from Eq. (14.14) with v_{ C }(t=0)=0:
14=\left(\frac{6 \times 10^{-3}}{0.1 \times 10^{-6} \times 1 \times 10^{3}}-\frac{200 \times 10^{-9}}{0.1 \times 10^{-6}}\right) t+6 \times 10^{-3}-1 k \Omega \times 600 \times 10^{-9}-0
which gives t = 241.3 ms.
(b) If R_{ x }=0 , the total output offset voltage will be due to the input offset voltage, the input biasing current, -I_{ B 2}=-I_{ B }+\left(I_{ io } / 2\right) , and the input offset current, and it can be found from Eq. (14.14) by replacing I_{ io } \text { by } I_{ B 2} . That is,
v_{ of }=\left(\frac{V_{ io }}{C_{ F } R_{1}}+\frac{I_{ B }-I_{ io } / 2}{C_{ F }}\right) t+V_{ io }-v_{ C }(t=0) (14.15)
The time required for the output voltage to reach the saturation level v_{\text {of }}=14 V can be found from Eq. (14.15) with v_{ C }(t=0)=0 :
14=\left(\frac{6 \times 10^{-3}}{0.1 \times 10^{-6} \times 1 \times 10^{3}}+\frac{400 \times 10^{-9}}{0.1 \times 10^{-6}}\right) t+6 \times 10^{-3}+0
which gives t = 218.7 ms.
