Question 8.25: Truth Table Develop the truth table of the two-input gate fo...
Truth Table
Develop the truth table of the two-input gate for the circuit shown in Figure 8.76(a). That is, determine the output voltage, V_{\text{out}}, in terms of inputs A and B when they are high (1) or low (0), for example, when both are 0, both are 1, and one is 0 and the other is 1. What is this operation?
It is clear that when both A and B are low (0), the NMOS will be OFF and the PMOS will be ON, thus, the output will be connected to the ground, i.e., the output will be low (0). This scenario is shown in Figure 8.76(b). When one of these inputs is high (1) and the other is low (0), the two series PMOSs block the output to be zero while one of the two parallel NMOSs allows connection to the V_{DD}. This scenario is shown in Figure 8.76(c). When both A and B are high (1), the output will be connected to V_{DD}, while the two PMOSs avoid connection to the ground. Thus, the output will be high (1) [see Figure 8.76(d)]. The solution is shown in Table 8.5. Based on this table, the output will be an OR gate (see Chapter 10).
| TABLE 8.5 The Truth Table for Figure 8.76(a) | ||
| A | B | A+B |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |