Question 9.1: Define a 2-bit synchronous up binary counter with an asynchr...
Define a 2-bit synchronous up binary counter with an asynchronous reset: (1) Write its state table and (2) state diagram. (3) Perform a logic implementation of the counter using positive edge-triggered JK flip-flops.
A 2-bit synchronous up binary counter is a 2-bit state machine. Upon clocking the state machine the counter will go through states 00, 01, 10, 11, and it will repeat that sequence of four states indefinitely, as long as it continues to be clocked. Figure 9.20 shows the state machine state diagram, while Table 9.10 depicts the state table of the 2-bit counter.
| Table 9.10 State table for the 2-bit counter of Example 9.1 | |||
| Clock | Present StateQ_1(t)Q_0(t) | Next StateQ_1(t+1)Q_0(t+1) | Async. Reset Input (Active high) Reset |
| ↑ | 0 0 | 0 1 | 0 |
| ↑ | 0 1 | 1 0 | 0 |
| ↑ | 1 0 | 1 1 | 0 |
| ↑ | 1 1 | 0 0 | 0 |
| 0 | X X | 0 0 | 1 |
The purpose of the asynchronous reset is for external logic to reset the state machine upon power-up. If there was no reset the initial state of the state machine after power-up is unpredictable; in other words with no reset initializing the flip-flop, one cannot predict which will be the starting state.
Note that the state machine Q_1 state bit is the MSB and Q_0 is the LSB. The state machine has an asynchronous input, its Reset which we can easily implement using the asynchronous reset of the flip-flops to be used. Note that the state machine upon Reset being negated and receiving clocks it will walk through states 00, 01, 10, 11, 00, . . . indefinitely. If at any time Reset goes high the state machine will abruptly go to state 00. Notice that all state transitions are conditioned by the Reset input, the present state and upon the reception of a clock the machine will move to its next state. Unfortunately, the state diagram does not show in a clean way the fact that Reset is asynchronous. If the design requirements would have been to do the same design with a synchronous Reset, the state diagram would not change. Usually in state machine design Reset is one of the few or sometimes the only asynchronous control signal in the system. It is customary to synchronize asynchronous signals into the clock domain of the state machine that one is dealing with. State machines in a general sense have two main parts, its sequential logic, that is the flip-flops that memorize the state Q(t). They also have their combinational logic, which is the logic used by the sequential portion of the machine to determine the inputs to the flip-flops that will generate the next state. Figure 9.21 depicts a high-level circuit diagram showing the state machine pieces. The block with the shape of a cloud represents combinational logic, or simply circuitry without memory. Note: having said that reset is needed to initialize the state of a machine, other methodologies are used to initialize state machines. One such method is designing scannable machines. All the state machine registers upon power on can be configured like a giant shift register and a known state is clocked in every flip-flop. Once all flip-flops are initialized the state machine is placed back in its normal operating mode and begins to run. For a good reference in scannable systems refer to [1].
By inspection of Figure 9.21 we can observe that the present state through the combinational logic produces the outputs for flip-flops 1 and 2 inputs. Reset as stated earlier is directly applied to the asynchronous reset input that we assume the JK flip-flops already have. So we need to come up with four logic equations, which are the equations of the flip-flop inputs as a function of the
present state. The equations follow:
J_1= f( Q_1, Q_0 ) (9.1)
K_1=g( Q_1, Q_0 ) (9.2)
J_0=h( Q_1, Q_0 ) (9.3)
K_0= i( Q_1, Q_0 ) (9.4)
With the present state information and the combinational logic the inputs to each flip-flop is presented so that upon the next active edge of the clock the state machine goes to its next state. So before doing the design we need a different form of the JK flip-flop characteristic table that facilitates the design process. Such new table is the JK flip-flop excitation table. Actually, the excitation table presents the same information provided by the characteristic table but in the following form: “What do the FF inputs need to be to make a transition from a determined present state to a desired next state when the active clock edge is present?” Review Table 9.6 with the JK FF characteristic table.
| Table 9.6 Negative edge triggered master/slave JK flip-flop characteristic table |
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| Clock | J | K | Q(t + 1) |
| ↓ | 0 | 0 | Hold (no change) |
| ↓ | 0 | 1 | 0 (Reset) |
| ↓ | 1 | 0 | 1 (Set) |
| ↓ | 1 | 1 | Complement (toggle) |
| 0 | X | X | Hold (no change) |
Using Table 9.6 we compose the excitation table for the JK FF. Table 9.11 depicts such excitation table.
| Table 9.11 JK FF excitation table | |||
| Present State | Next State | JK FF inputs | |
| Q(t) | Q(t+1) | J | K |
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
It is important to emphasize that since the excitation table has a present state and a next state column without showing the clock explicitly, the same table applies to positive as well as to negative edge-triggered devices. Let us recall from the previous chapter that X refers to a don’t care condition, either a 1 or a 0.
