Question 13.9: Logic Circuit Design Using Karnaugh Maps Design a logic circ...
Logic Circuit Design Using Karnaugh Maps
Design a logic circuit that implements the truth table of Figure 13.36.
Known Quantities: Truth table for y(A, B, C, D).
Find: Realization of y.
Assumptions: Two-, three-, and four-input gates are available.
Analysis: We use the Karnaugh map of Figure 13.37, which is shown with values of 1 and 0 already in place. We recognize four subcubes in the map; three are four-cell subcubes, and one is a two-cell subcube. The expressions for the subcubes are: \bar{A} \cdot \bar{B} \cdot \bar{D} for the two-cell subcube; \bar{B} \cdot \bar{C} for the subcube that wraps around the map; \bar{C} \cdot D for the four-by-one subcube; and A \cdot D for the square subcube at the bottom of the map. Thus, the expression for y is:
y=\bar{A} \cdot \bar{B} \cdot \bar{D}+\bar{B} \cdot \bar{C}+\bar{C} D+A D .
The implementation of the above function with logic gates is shown in Figure 13.38.
Comments: The Karnaugh map covering of Figure 13.37 is a sum-of-products expression because we covered the map using the ones.
