Question 9.1: A 4-bit asynchronous binary counter is shown in Figure 9–8(a...
A 4-bit asynchronous binary counter is shown in Figure 9–8(a). Each D flip-flop is negative edge-triggered and has a propagation delay for 10 nanoseconds (ns). Develop a timing diagram showing the Q output of each flip-flop, and determine the total propagation delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q_{3}. Also determine the maximum clock frequency at which the counter can be operated.
The timing diagram with delays omitted is as shown in Figure 9–8(b). For the total delay time, the effect of CLK8 or CLK16 must propagate through four flip-flops before Q_{3} changes, so
t_{p(tot)} = 4 × 10 ns = 40 ns
The maximum clock frequency is
f_{max} = \frac{1}{t_{p(tot)}} = \frac{1}{40 ns} = 25 MHz
The counter should be operated below this frequency to avoid problems due to the propagation delay.