Question 10.14: J-K Flip-Flop Create a J-K flip-flop using the block design ......
J-K Flip-Flop
Create a J-K flip-flop using the block design method. Right-click in the block design area and insert the symbol named jkff. Test the design by creating a waveform simulation file. Repeat using the VHDL design entry method.
Figure 10–41 shows the solution as a bdf file using the primitive symbol JKFF. This symbol is a positive-edge flip-flop so an inverter was added to the clock line to make it a negative edge trigger and n_cp is used to represent {\overline{{C_{p}}}}.
The VHDL solution is shown in Figure 10–42(a). Notice in the entity that q is declared as a BUFFER to enable it to be used as both an input and an output. This is because the output assigned to q is sometimes determined by the state that is input to it from the previous value of q. [i.e., for the Hold condition, q becomes the state that q was before the clock transition (no change), and for Toggle, it becomes the opposite state]. The CASE statement is going to be checking a 2-bit vector called jk so a vector SIGNAL must be declared, and the individual j and k inputs must be concatenated together using the & symbol to form a 2-bit vector. The IF statement checks for a negative edge on cp. If it is a negative edge, then the CASE block is executed. All four flip-flop conditions are listed as the CASE conditions. The OTHERS clause is required to cover the other states allowed by std_logic besides 1 and 0.
The flowchart for the process is shown in Figure 10–42(b). This makes it obvious that the CASE statement is only executed if there is a negative edge on cp. If not, q is unaffected and the process ends.
The simulation file is shown in Figure 10–43. This simulation must be run for both design methods (block and VHDL) to check the validity of both implementations. [Follow the procedure outlined in Section 4– 4 (Steps 38–40) to assign the bdf file, then the vhd file to the current project before each simulation.] This simulation illustrates the four operations of a J-K flipflop. At the first negative clock edge, j and k are both LOW (Hold) so q remains unchanged. At the next edge, j is HIGH, k is LOW, so q is Set. At the next edge, j is LOW, k is HIGH, so q is Reset. For the last two negative clock edges, j and k are both HIGH so q toggles to the opposite state each time.
