Question 13.8: Use the structured programming approach to design a 4-bit sy......

Digital Electronics A Practical Approach with VHDL [1368739]

Use the structured programming approach to design a 4-bit synchronous counter using component instantiations as shown in Figure 13–43.

Figure 13–43

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The VHDL solution for the 4-bit synchronous counter using component instantiations is given in Figure 13–44(a). You will notice that the J-K flip-flop component ( jk_ ff ) was taken from the program written for Example 10–14. The ARCHITECTURE of sync_count uses four instances of jk_ ff. An internal SIGNAL was required for defining the signals vcc (which is set to ‘1’ for input to the first jk_ ff ) and x and y (which are the outputs of internal AND gates.)
Figure 13–45 shows the simulation of the circuit counting from 0000 up to 1111 on the q-outputs.

Figure 13–44

Figure 13–45

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