Question 18.3: A 2N5486 n-channel JFET has VP = -6 V and IDSS = 8 mA. Use t......
A 2N5486 n-channel JFET has V_{P} = -6 V and I_{DSS} = 8 mA . Use the device’s transfer characteristic to design a biasing arrangement such that, when used with a supply voltage of 15 V and a drain resistor of 2.5 kΩ, the amplifier has a quiescent output voltage of 10 V.
A suitable circuit is given below.
From Equation 18.3 we know that
I_{D} = I_{DSS}\left(1 – \frac{V_{GS}}{V_{P}} \right)^{2}which, using the figures given for V_{P} and I_{DSS} , may be plotted to give
The quiescent output voltage V_{o(quiescent)} is given by
V_{o(quiescent)} = V_{DD} – V_{R}where V_{R} is the voltage drop across the drain resistor R_{D} . Therefore, the required value of V_{R} is given by
V_{R} = V_{DD} – V_{o(quiescent)} = 15 – 10 = 5 Vand the required quiescent drain current I_{D(quiescent)} is
I_{D(quiescent)} = \frac{V_{R}}{R_{D}} = \frac{5 V}{2.5 kΩ} = 2 mAFrom the transfer characteristic, this value of drain current corresponds to a gate-tosource voltage of -3 V. As the gate is at ground potential, this gate-to-source voltage must be obtained by a voltage drop across R_{S} of +3 V. Thus, the value of R_{S} is given by
R_{S} = \frac{V_{GS}}{I_{D}} = \frac{3 V}{2 mA} = 1.5 kΩThe value of R_{G} is not critical as it is simply required to bias the gate to zero volts. It would normally be chosen to give a high input resistance, but must not be so high that the voltage drop caused by the effects of the gate current (a few nanoamps) become significant. A value of 470 kΩ would be suitable.
