Question 16.21: (a) Draw the flowchart of PLD design, programming and test p......

(a) When PLDs were first introduced the logic designer would develop a fuse map that showed which fuses to blow and send it off to the PROM, PAL or FPLA manufacturer. The manufacturer would then program the device according to the fuse map, test it and send it to the designer. In recent years the availability of relatively inexpensive programming equipment has made it convenient for users to program their own PLDs. There are universal programmers on the market that can program most common PROMs, PALs, and FPLAs. The device to be programmed is plugged into a socket on the programmer, and the programmer will program and test the device according to data that have been supplied by the user.

The programming and test data are typically developed using commonly available software that will run on standard PCs. Using this software, the user enters data into the computer describing the logic functions he wants programmed into the PLD, as well as information on how the device is to be tested. The software then generates a fuse map and test data in a form that can be sent over a cable to the PLD programmer’s memory. Once the programmer has the data, it can proceed to program and test the device. When finished, the programmer will indicate whether the device has passed or failed the testing procedure. If it passes, it can be removed from the programer’s socket and placed in the prototype circuit for further testing.

Figure. 16.17 is a flowchart showing the various steps in the process of designing, programming and testing a PLD.

(b) Figure 16.18 shows the cells structure of the Xilinx XC 2000 FPGA, one of the simplest FPGAs produced by the manufactures. The look-up table is a small user programmable memory that takes as its address the inputs to the cells. The table can be programmed to implement any logic function in a manner similar to a PROM. More sophisticated devices have much more complex logic cells that may contain several flip-Flops, several look-up tables and a selection of other logic gates. The versatility of this arrangement, and the very flexible interconnection mechanism, allow complex circuits to be implemented within a single chip.