Question 11.9: CMOS Gate Determine the logic function implemented by the CM......

Find: v_{out} for each of the four combinations of v_{1} and v_{2} .

Schematics, Diagrams, Circuits, and Given Data: V_{T}  =  1.7  V ; V_{DD}  =  5  V.

Assumptions: Treat the MOSFETs as open circuits when off and as linear resistors when on.

Analysis:

1. v_{1}  =  v_2  =  0  V. With both input voltages equal to zero, neither M_{3} nor M_{4} can conduct, since the gate voltage is less than the threshold voltage for both transistors. Both M_{1} and M_{2} will similarly be off, and no current will flow through the drain-source circuits of M_{1} and M_{2} . Thus, v_{out}  =  V_{DD}  =  5  V . This condition is depicted in Figure 11.21.
2. v_{1}  =  5  V  ;  v_2  =  0  V. Now M_{2} and M_{4} are off because of the zero gate voltage, while M_{1} and M_{3} are on. Figure 11.22(a) depicts this condition. Thus, v_{out}  =  0.
3. v_{1}  =  5  V  ;  v_2  =  0  V. By symmetry with case 2, we conclude that v_{out}  =  0.
4. v_{1}  =  5  V  ;  v_2  =  5  V . Now both M_{1} and M_{2} are open circuits, and therefore v_{out}  =  0 .

These results are summarized in the table below. The output voltage for case 4 is sufficiently close to zero to be considered zero for logic purposes.

Thus, the gate is a NOR gate.

Comments: While exact analysis of CMOS gate circuits could be tedious and involved, the method demonstrated in this example—to determine whether transistors are on or off—leads to very simple analysis. Since in logic devices one is interested primarily in logic levels and not in exact values, this approximate analysis method is very appropriate.