Question 3.1: Design the Pierce oscillator in Figure 3.3(a) to oscillate a......

Selecting the Q point at I_{D} = 6 mA and V_{D S} = 10V, and using V_{D D} = 20V it follows from

I_{D}=I_{D S S}\left(1-\frac{V_{G S}}{V_{P}}\right)^{2}

that V_{G S} ≈ −1V and

g_{m}={\frac{2I_{D S S}}{V_{\rho}^{2}}}\left(V_{G S}-V_{P}\right)={\frac{2\left(12  \times  10^{-3}\right)}{\left(3.5\right)^{2}}}\left(-1+3.5\right)\approx5~{\mathrm{mS}}~~~

The output resistance can be calculated in terms of the channel modulation voltage \mathbf{}V_{\mathrm{}M} (similar to the Early voltage) as

r_{o}={\frac{V_{M}}{I}}

which for I_{D} = 6 mA a typical r_{o} is 50 kΩ.

The values of  R_{S}{\mathrm{~and~}}R_{D} are

R_{S}={\frac{-V_{G S}}{I_{D}}}={\frac{1}{6  \times  10^{-3}}}=164\Omega

and

R_{D}={\frac{V_{D D}-V_{D S}-I_{D}R_{S}}{I_{D}}}={\frac{20-10-1}{6  \times  10^{-3}}}=1.47\mathrm{~k\Omega}

The capacitor {{C}}_{2} is in parallel with the transistor’s output terminals. The transistor has a few picofarads of output capacitance (C_{o u t}) between its source and drain. This output capacitance can be neglected if { C}_{2}\gg{ C}_{o u t}. Several values of {{C}}_{2}, and the approximate value of |X_{C_{2}}|, that satisfy { C}_{2}\gg{ C}_{o u t}. are listed in Table 3.1.

Two design procedures are considered. First, assuming that the loss resistance of the inductor is negligible (i.e.,{{R}}_{s} = 0), and second with R_{s}\neq0.

If {{R}}_{s} = 0, (3.16) gives

g_{m}r_{d}\geq\frac{X_{2}(\omega_{o})}{X_{1}(\omega_{o})}=\frac{C_{1}}{C_{2}}                                        (3.16)

g_{m}r_{d}=0.05(50\times10^{3})=250\gt {\frac{C_{1}}{C_{2}}}

Letting {{C}}_{2} = 1.6 nF, it follows that

C_{1}\lt 250(1.6\times10^{-9})=0.4~\mu\mathrm{{F}}

The inequality can be satisfied with {C}_{1} = 100 nF.

From (3.15), with C_{T}\approx C_{2}=1.6\ {nF}, the value of the inductor is 15.8 μH. If R_{s}\neq0. Table 3.2 illustrates the calculation of L for {{C}}_{2} = 1.6 nF with \textstyle C_{1} = 100 nF, and also for {{C}}_{2} = 16 nF with \textstyle C_{1} = 20 nF. Typical values of the unloaded Q (i.e., Q_{U}=\omega L/R_{s} ) for the inductor are listed with the associated R_{s}. Finally, the inequality in (3.26) is checked.

\omega_{o}={\frac{1}{\sqrt{L C_{T}}}}                                (3.15)

g_{m}r_{d}\gt \frac{X_{2}^{2}(\omega_{o})  +  r_{d}R_{s}}{X_{1}(\omega_{o})X_{2}(\omega_{o})}                                  (3.26)

The above calculations show that the assumption R_{s} = 0 will not work in this case. Of course, when using the design procedure based on R_{s} = 0 there are values for which (3.26) is not satisfied and, therefore, oscillations will not occur.

The calculations also show that if the inductor’s { Q}_{U} is 30 (i.e., R_{s} = 0.6Ω) the oscillator will not work. However, if { Q}_{U} is increased to 50 the oscillation conditions are satisfied. Also, the inequality (3.26) is better satisfied with a higher value of {g}_{m}. This can be attained by designing the oscillator with V_{G S} = −0.5V so that {g}_{m} = 6 mS.

The simulation of the oscillator with \mathbf{C}_{1} = 20 nF, {{C}}_{2} = 16 nF, and L = 2.86 μH ({ Q}_{U} = 50) is shown in Figure 3.4(a). The Q point is at I_{D} = 5.68 mA and V_{D S} = 10.6V. The resulting oscillation at 999.9 kHz is shown in Figure 3.4(b). Although not shown, the simulation was also performed by designing the circuit with V_{G S} = −0.5V and I_{D} = 6 mA.

From a practical point of view, the above calculation (based on typical transistor parameters) shows that (3.26) is ‘‘barely’’ satisfied (250 > 228). This information is especially useful if many units are to be constructed since the spread of the transistor’s parameters might affect the yield. Hence, the designer can use the statistical analysis tools, or might redesign the oscillator using a transistor with a higher g_{m}.