Question 29.14: Determine the clock frequency needed to form an 8-bit, singl......

CMOS Circuit Design, Layout, and Simulation [1366181]

Determine the clock frequency needed to form an 8-bit, single-slope converter, if the analog signal bandwidth is 20 kHz.

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Since the sampling rate required is 40 kHz, then the worst-case situation would occur for a full-scale input, in which event the integrator output would have to climb to its maximum value and the counter would increment $2^{N}$ times during the corresponding 25 μs period between samples. Therefore, the clock frequency would need to be $2^{N}$ times faster than the sampling rate or 10.24 MHz.

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