Question 9.39: Discuss the specifications of PMOS, NMOS, and CMOS logic gat......

PMOS and NMOS logic gates typically use a supply of 10 \mathrm{~V}, but can operate with lower or higher supply voltages. Using a 5 \mathrm{~V} supply, power dissipation is approximately 0.25 \mathrm{~mW} per gate, and noise margin is 1.5 \mathrm{~V}. Because there is no input current to MOSFET devices, there should be no limit to dc fan-out for PMOS and NMOS logic gates. But gate inputs do have capacitance, and each additional gate input connected as a gate output terminal slows down the switching speed of the gate. A fan-out of 50 is considered a normal maximum. Propagation delay time is around 50 \mathrm{~ns} for NMOS and 100 \mathrm{~ns} for PMOS. The relatively large switching time is due to the high output resistance, approximately 2  \mathrm{k} \Omega, which is 20 times the typical R_{o} of 100 \Omega for TTL. For a given load capacitance (typically, 15 \mathrm{pF} is used when testing for t_{r} ), an NMOS gate will be 20 times slower than TTL.

Although the integrated circuit fabrication process for CMOS is more complicated than that for PMOS or NMOS, CMOS has the very important advantage that its power dissipation per gate is much less than that for any other logic family. (integrated injection logic can be an exception to this). Other advantages are: (1) operation from supply voltages as low as 1 \mathrm{~V}, (2) fan-out in excess of 50, and (3) excellent noise immunity.