Question 16.18: Draw the block diagram of a typical CPLD....

PLAs, PALs and equivalent reprogrammable devices such as GALs and EPLDs are often collectively referred to as simple programmable logic devices (SPLDs). Complex PLDs can be thought of as an arrangement of several SPLDs within a single chip. In addition to providing a large number of array elements they also provide a powerful method of interconnecting inputs and outputs to allow fairly complex circuits to be implemented within a single package. The block diagram of a typical CPLD configuration is given in Fig. 16.15.

CPLDs are normally implemented using EPROM or EEPROM techniques rather than fuses and are thus reprogrammable. EEPROM parts have the advantage of in-circuit reprogrammability, allowing their functionality to be changed without the devices being removed from the board. This is particularly useful when performing system upgrades.

At present devices with several thousands of gates are available, with delay times of only a few seconds. The propagation delay time can be predicted while implementing the design. A single CPLD might typically be used to implement a mixture of registers, decoders, multiplexers and counters. For example, a 32-bit counter can be produced using a single device.