Question 22.1: Estimate the maximum and minimum voltage on the gate of M1 i......
Estimate the maximum and minimum voltage on the gate of M1 in Fig. 22.2 that ensures that neither M1 or M2 shut off. Verify your hand calculations with SPICE simulations.
Note that the diff-amp tail current, I_{SS} , is 40 μA (the widths of the MOSFETs were doubled from the sizes indicated in Table 9.1). When \nu_{I1}=\nu_{I2}=2.5\ V, the differential input voltage, \nu_{DI}, is 0 and the current flowing in M1 and M2 is 20 μA (=i_{D1}=i_{D2}).
Using Eq. (22.7), we can estimate the maximum voltage on the gate of M1 as
\nu_{DIM A X}\lt \nu_{I1}-\nu_{I2}=\sqrt{\frac{2\cdot L\cdot I_{S S}}{K P_{n}\cdot W}} (22.7)
\nu_{I1M AX}=\sqrt{\frac{2\cdot L\cdot I_{S S}}{K P_{n}\cdot W}}\,+\nu_{I2}=\sqrt{\frac{2\cdot2\cdot40}{120\cdot10}}\,+2.5=2.865\ Vor \nu_{I1} is 365 mV above \nu_{I2}. The minimum voltage allowed on the gate of M1 (to keep some current flowing in M1) is then 365 mV below \nu_{I2} or 2.135 V. The simulation results are seen in Fig. 22.3. Notice how, when the inputs are equal (both are 2.5 V), the currents in M1 and M2 are equal and approximately 20 μA (=I_{SS}/2).
Table 9.1 Typical parameters for analog design using the long-channel CMOS process discussed in this book. Note that the parameters may change with temperature or drain-to-source voltage (e.g., Fig. 9.24).
Long-channel MOSFET parameters for general analog design
VDD = 5 V and a scale factor of 1 μm (scale = 1e-6)
| Parameter | NMOS | PMOS | Comments |
| Bias current, I_D | 20 \mu A | 20 \mu A | Approximate |
| W/L | 10/2 | 30/2 | Selected based on I_D\ \text{and}\ V_{DS,sat} |
| V_{DS,sat}\ \text{and}\ V_{SD,sat} | 250 mV | 250 mV | For sizes listed |
| V_{GS}\ \text{and}\ V_{SG} | 1.05 V | 1.15 V | No body effect |
| V_{THN}\ \text{and}\ V_{THP} | 800 mV | 900 mV | Typical |
| \partial V_{THN,P}/\partial T | -1\ \text{mV/C°} | -1.4\ \text{mV/C°} | Change with temperature |
| KP_n\ \text{and}\ KP_p | 120\ \mu A/V^2 | 40\ \mu A/V^2 | t_{ox}=200\ \mathring{A} |
| C_{o x}^{\prime}=\varepsilon _{o x}/t_{o x} | 1.75fF/\mu m^2 | 1.75fF/\mu m^2 | C_{ox}=C_{o x}^{\prime}WL\cdot (scale)^2 |
| C_{oxn}\ \text{and}\ C_{oxp} | 35fF | 105fF | PMOS is three times wider |
| C_{gsn}\ \text{and}\ C_{sgp} | 23.3fF | 70fF | C_{gs}=\frac{2}{3}C_{ox} |
| C_{gdn}\ \text{and}\ C_{dgp} | 2fF | 6fF | C_{gd}=CGDO\cdot W\cdot scale |
| g_{mn}\ \text{and}\ g_{mp} | 150\ \mu A/V | 150\ \mu A/V | At\ I_D=20\ \mu A |
| r_{on}\ \text{and}\ r_{op} | 5\ M\Omega | 4\ M\Omega | Approximate at I_D=20\ \mu A |
| g_{mn}r_{on}\ \text{and}\ g_{mp}r_{op} | 750 V/V | 600 V/V | Open circuit gain |
| \lambda _n\ \text{and}\ \lambda _p | 0.01\ V^{-1} | 0.0125\ V^{-1} | At L = 2 |
| f_{Tn}\ \text{and}\ f_{Tp} | 900 MHz | 300 MHz | \text{For}\ L=2,f_T\ \text{goes up if}\ L=2 |
