Question 9.40: Explain the working of CMOS NAND and NOR gates. Give its spe......
Explain the working of CMOS NAND and NOR gates. Give its specifications.
Consider the CMOS NAND gate shown in Fig. 9.37(a). The parallel-connected transistors Q_{1} and Q_{2} are Pchannel MOSFETs and the series-connected devices Q_{3} and Q_{4} are N-channel MOSFETs. When input terminals A and B are grounded, the gates of Q_{1} and Q_{2} are negative with respect to the source terminals. Therefore, Q_{1} and Q_{2} are biased ON. Also the gates of Q_{3} and Q_{4} are at the same potential as the device source terminals, and consequently Q_{3} and Q_{4} are OFF. Depending on the actual load current and the values of R_{D(\text { on) }}, there will be a small voltage drop along the channels of Q_{1} and Q_{2}. Thus, the output voltage V_{o} is close to the level of the supply voltage.
When a HIGH positive input voltage (equal to 0.7 V_{D D} or greater) is applied to terminal B, Q_{4} is biased \mathrm{ON} and Q_{2} is biased OFF. However, with terminal A still grounded, Q_{3} remains \mathrm{OFF}, Q_{1} is still \mathrm{ON}, and the output voltage remains at V_{o} \approx V_{D D}. When HIGH inputs are applied to terminal A AND terminal B, both P-channel devices \left(Q_{1}\right. and \left.Q_{2}\right) are biased OFF, and both N-channel MOSFETs \left(Q_{3}\right. and \left.Q_{4}\right) are biased ON. The output now goes to V_{o} \approx 0 \mathrm{~V}.
The circuit of a CMOS NOR gate is shown in Fig. 9.34(b). Once again two P-channel devices \left(Q_{1}\right. and \left.Q_{2}\right) and two \mathrm{N}-channel devices \left(Q_{3}\right. and \left.Q_{4}\right) are employed. When both inputs are at ground level, Q_{3} and Q_{4} are biased OFF, and Q_{1} and Q_{2} are ON. In this condition there is about a 10 \mathrm{mV} drop from drain to source terminals in P-channel transistors, and V_{o} is very close to V_{D D}. When terminal A has a HIGH positive input, Q_{1} switches OFF and Q_{3} switches ON. The series combination of Q_{1} and Q_{2} is now open circuited, and the output is shorted to ground via Q_{3}. Similarly, if terminal A remains grounded, and terminal B has a \mathrm{HIGH} input applied, Q_{2} switches OFF and Q_{4} switches ON. Again, the output goes to ground level.
