Question 11.7: MOSFET DC Motor Drive Circuit The aim of this example is to ......
MOSFET DC Motor Drive Circuit
The aim of this example is to design a MOSFET driver for the Lego { }^{\circledR} 9V Technic motor, model 43362. Figures 11.15(a) and (b) show the driver circuit and a picture of the motor, respectively. The motor has a maximum (stall) current of 340 mA. Minimum current to start motor rotation is 20 mA. The aim of the circuit is to control the current to the motor (and therefore the motor torque, which is proportional to the current) via the gate voltage.
Known Quantities: Transistor large-signal parameters; component values.
Find: Values of R_1 and R_2 .
Schematics, Diagrams, Circuits, and Given Data: Figure 11.15. V_T = 1.2 V; K = 0.08 A/V² .
Assumptions: Assume that the MOSFET is in the saturation region.
Analysis: The conditions for the MOSFET to be in the saturation region are: v_{GS} \gt V_T and v_{GD} \lt V_T . The first condition is satisfied whenever the gate voltage is above 1.2 V. Thus the transistor will first begin to conduct when V_G = 1.2 . Assuming for the moment that both conditions are satisfied, and that V_{DD} is sufficiently large, we can calculate the drain current to be:
i_D = K(v_{GS} − V_T )^2 = 0.08 \times (v_G − 1.2)^2 A
The plot of Figure 11.15(c) depicts the DC motor (drain) current as a function of the gate voltage. You can see that the maximum current of 340 mA can be generated with a gate voltage of approximately 3.3 V. It would take approximately 1.5 V at the gate to generate the minimum required current of 20 mA.
Comments: This circuit could be quite easily implemented in practice to drive the motor with a signal from a microcontroller. In practice, instead of trying to output an analog voltage, a microcontroller is better suited to the generation of a digital (On-Off) signal. For example, the gate drive signal could be a pulse-width modulated (PWM) 0–5 V pulse train, in which the ratio of the On time to the period of the waveform time is called duty cycle. Figure 11.15(d) depicts the possible appearance of a digital PWM gate voltage input.
