Question 29.15: Perform the operation of a 3-bit successive approximation AD......
Perform the operation of a 3-bit successive approximation ADC similar to Fig. 29.36 with V_{REF} = 8. Make a table that consists of D_2D_1D_0,\ B_2B_1B_0,\ V_{OUT} (the output from the DAC) and the comparator output, which shows the binary search algorithm of the converter for \nu_{IN} = 5.5 V and 2.5 V.
We will designate D_2,D_1,D_0, as the initial output of the SAR before the comparator makes its decision. The final value is designated as D_2D_1D_0. Notice that if the comparator is a 1, D_2,D_1,D_0, differs from D_2D_1D_0, but if the comparator outputs a 0, then D_2,D_1,D_0, = D_2D_1D_0. The output of the shift register is designated as B_2B_1B_0.
Following the algorithm discussed previously, initially \nu_{IN} = 5.5 V and is compared with 4 V. Since the comparator output is 0, the MSB remains a 1. The next bit is examined, and the output of the DAC is now 6 V. Since V_{OUT} > \nu_{IN}, the comparator output is 1, which resets the current SAR bit, D_1, to a 0 at the end of period T2. Lastly, the LSB is examined, and \nu_{IN} is compared with 5 V. Since \nu_{IN} > V_{OUT}, the comparator output is a 0, and the current SAR bit, D_0, remains a 1. The results can be examined in Fig. 29.38a. The final value for D_2D_1D_0 is 101, which is what is expected considering that 101 in binary is equivalent to 5_{10}. Figure 29.38b shows the data for the ADC using \nu_{IN} = 2.5 V. The final value for \nu_{IN} = 2.5 is 010, which again is what is expected for 3-bit resolution.
