Question 29.15: Perform the operation of a 3-bit successive approximation AD......
Perform the operation of a 3-bit successive approximation ADC similar to Fig. 29.36 with V_{{RE F}}=8 . Make a table that consists of D_{2}D_{1}D_{0},\ B_{2}B_{1}B_{0},\ V_{OU T} (the output from the DAC) and the comparator output, which shows the binary search algorithm of the converter for {{v}}_{I N} = 5.5 V and 2.5 V.
We will designate D_{2},D_{1},D_{0}. as the initial output of the SAR before the comparator makes its decision. The final value is designated as D_{2}D_{1}D_{0}. Notice that if the comparator is a 1, D_{2},D_{1},D_{0}, differs from D_{2}D_{1}D_{0}, but if the comparator outputs a 0, then D_{2},D_{1},D_{0}, = D_{2}D_{1}D_{0}. The output of the shift register is designated as B_{2}B_{1}B_{0}.
Following the algorithm discussed previously, initially v_{I N}\:=5.5\ V and is compared with 4 V. Since the comparator output is 0, the MSB remains a 1. The next bit is examined, and the output of the DAC is now 6 V. Since V_{ O U T}\gt v_{I N}, the comparator output is 1, which resets the current SAR bit, { D}_{1}, to a 0 at the end of period T2. Lastly, the LSB is examined, and v_{I N} is compared with 5 V. Since v_{I N}\gt V_{ O U T}, the comparator output is a 0, and the current SAR bit, { D}_{0}, remains a 1. The results can be examined in Fig. 29.38a. The final value for D_{2}D_{1}D_{0} is 101, which is what is expected considering that 101 in binary is equivalent to 5_{10}. Figure 29.38b shows the data for the ADC using v_{I N}\:=2.5\ V. The final value for v_{I N}\:=2.5\ V is 010, which again is what is expected for 3-bit resolution.
