Question 30.16: Repeat Ex. 30.10 if 1.5 bits/stage are used. Assume the conv......
Repeat Ex. 30.10 if 1.5 bits/stage are used. Assume the converter is ideal and the comparators switch precisely at V_{_{C M}}/2 (= 250 mV here) and 3V_{_{C M}}/2 (= 750 mV here). Assume all latches initially contain zeroes.
Step-by-Step
\begin{aligned} &v_{in} \quad\quad\quad \quad\quad\quad\quad a_{1.5x}b_{1.5x} \quad v_{out} \quad\quad\quad\quad\quad\quad\quad\quad \text{Digital out}\\ & 600 \ \mathrm{mV}(N-1=7) \quad\quad 01 \quad \quad700 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_7=\overline{a_{1.57}} b_{1.57} \oplus a_{1.56} \oplus c_6=0 \\ \\ & c_7=\overline{a_{1.57}} b_{1.57} a_{1.56}+c_6\left(\overline{a_{1.57}} b_{1.57}+a_{1.56}\right)=1 \\\\ & 700 \ \mathrm{mV}(N-2=6) \quad\quad 01 \quad\quad 900 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_6=\overline{a_{1.56}} b_{1.56} \oplus a_{1.55} \oplus c_5=0 \\\\ & c_6=\overline{a_{1.56}} b_{1.56} a_{1.55}+c_5\left(\overline{a_{1.56}} b_{1.56}+a_{1.55}\right)=1 \\\\ & 900 \ \mathrm{mV}(N-3=5) \quad\quad 11 \quad\quad 300 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_5=\overline{a_{1.55}} b_{1.55} \oplus a_{1.54} \oplus c_4=0 \\\\ & c_5=\overline{a_{1.55}} b_{1.55} a_{1.54}+c_4\left(\overline{a_{1.55}} b_{1.55}+a_{1.54}\right)=0 \\\\ & 300 \ \mathrm{mV}(N-4=4) \quad\quad 01 \quad\quad 100 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_4=\overline{a_{1.54}} b_{1.54} \oplus a_{1.53} \oplus c_3=1 \\\\ & c_4=\overline{a_{1.54}} b_{1.54} a_{1.53}+c_3\left(\overline{a_{1.54}} b_{1.54}+a_{1.53}\right)=0 \\\\ & 100 \ \mathrm{mV}(N-4=3) \quad\quad 00 \quad\quad 700\ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_3=\overline{a_{1.53}} b_{1.53} \oplus a_{1.52} \oplus c_2=1 \\\\ & c_3=\overline{a_{1.53}} b_{1.53} a_{1.52}+c_2\left(\overline{a_{1.53}} b_{1.53}+a_{1.52}\right)=0 \\\\ & 700 \ \mathrm{mV}(N-6=2) \quad\quad 01 \quad\quad 900 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_2=\overline{a_{1.52}} b_{1.52} \oplus a_{1.51} \oplus c_1=0 \\\\ & c_2=\overline{a_{1.52}} b_{1.52} a_{1.51}+c_1\left(\overline{a_{1.52}} b_{1.52}+a_{1.51}\right)=1 \\\\ & 900\ mV\ (N- 7 = 1)\quad\quad 11 \quad\quad 300 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_{1}={\overline{{a_{1.51}}}}b_{1.51}\oplus\ c_{0}=0\\\\ & c_{1}=\overline{{{a_{1.51}}}}b_{1.51}a_{1.50}+c_{0}(\overline{{{a_{1.51}}}}b_{1.51}+a_{1.50})=0 \\\\ & 300\ mV\ (N- 8 = 0)\quad\quad 01 \quad\quad 100 \ \mathrm{mV} \quad\quad\quad\quad\quad\quad b_{0}={\overline{{a_{1.50}}}}b_{1.50}=1 \\\\ & c_{0}=a_{1.50}=0 \end{aligned}
noting that b_{8}=a_{1.57}\oplus c_{7}=1. We can reorder the bits so the MSB is on the left, the LSB is on the right, yielding 1 0001 1001 and subtract 0 0111 1111 yielding
1 0001 1001 (281)
– 0 0111 1111 (127)
0 1001 1010 (154)
This is the result given in Ex. 30.10 (1001 1001, or decimal 153) plus 1 LSB. The 1 LSB discrepancy can be traced to Eq. (30.66) where we used 0.5 LSBs. Because our resolution is at best 1 LSB, sometimes the result will experience a round-off error. To understand this in the subtraction above, the more correct decimal representation of V_{C M}-0.5 LSBs is 127.5 and the more correct decimal output is 153.5.
v_{in}= a_{1.5N-1} \cdot 2V_{CM} + (\overline{a_{1.5N-1}} b_{1.5N-1} + a_{1.5N-2}) \cdot V_{CM} + (\overline{a_{1.5N-2}}b_{1.5N-2} + a_{1.5 N-3}) \cdot \frac{V_{CM}}{2} + (\overline{a_{1.5N-3}} b_{1.5 N-3} + a_{1.5N-4}) \cdot \frac{V_{CM}}{4} + … + \overline{a_{1.50}}b_{1.50} \cdot \frac{V_{CM}}{2^{N-1}} – (V_{CM} – 0.5 LSB) \quad \quad (30.66)Related Answered Questions
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